User manual

Chapter 5 Register Descriptions

13 LADIR Extender Logical Address Window Direction

When this bit is set, the address range defined by

LASIZE[2:0] and LABASE[7:0] applies to

MXIbus cycles that are mapped in to VXIbus

cycles (inward cycles). When this bit is cleared,

the range applies to VXIbus cycles that are

mapped out to MXIbus cycles (outward cycles).

The complement of the defined range is mapped

in the opposite direction. This bit is cleared by a

hard reset and is not affected by a soft reset.

12-11 1 Reserved

These bits are reserved. They return 11 (binary)

when the VWR0 is read. These bits can be

written with any value.

10-8 LASIZE[2:0] Extender Logical Address Window Size

These bits define the size of the range of logical

addresses that map through the Extender Logical

Address Window. They specify the number of

address lines that are compared to the

LABASE[7:0] bits when determining if a

VXIbus configuration access is in the mapped

range. The LASIZE[2:0] most significant bits of

LABASE[7:0] are compared, while the

remaining bits are ignored. Thus, the number of

logical addresses in the range mapped is

8-LASIZE[2:0]

. These bits are cleared by a hard

reset and are not affected by a soft reset.

7-0 LABASE[7:0] Extender Logical Address Window Base

These bits define the base address of the range of

logical addresses that map through the Extender

Logical Address Window. They correspond to

address lines 13 through 6, which effectively

makes them the logical address lines. These bits

can be thought of as the base logical address of

the range that maps through the VXI-MXI-2.

These bits are cleared by a hard reset and are not

affected by a soft reset.