User manual

Chapter 5 Register Descriptions
© National Instruments Corporation 5-19 VXI-MXI-2 User Manual
13 A32DIR Extender A32 Window Direction
When this bit is set, the address range defined by
A32SIZE[2:0] and A32BASE[7:0] applies to
MXIbus cycles that are mapped in to VXIbus
cycles (inward cycles). When this bit is cleared,
the range applies to VXIbus cycles that are
mapped out to MXIbus cycles (outward cycles).
The complement of the defined range is mapped
in the opposite direction. This bit is cleared by a
hard reset and is not affected by a soft reset.
12-11 1 Reserved
These bits are reserved. They return 11 (binary)
when the VWR3 is read. These bits can be
written with any value.
10-8 A32SIZE[2:0] Extender A32 Window Size
These bits define the size of the range of A32
addresses that map through the Extender A32
Window. They specify the number of address
lines that are compared to the A32BASE[7:0]
bits when determining if a VMEbus A32 access
is in the mapped range. The A32SIZE[2:0] most
significant bits of A32BASE[7:0] are compared,
while the remaining bits are ignored. Thus, the
number of A32 addresses in the range mapped is
16777216 * 2
8-A32SIZE[2:0]
. These bits are
cleared by a hard reset and are not affected by a
soft reset.
7-0 A32BASE[7:0] Extender A32 Window Base
These bits define the base address of the range of
A32 addresses that map through the Extender
A32 Window. They correspond to address lines
31 through 24 (the eight most significant address
lines in VMEbus A32 space). These bits are
cleared by a hard reset and are not affected by a
soft reset.