User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-20 © National Instruments Corporation
VXIbus Interrupt Configuration Register (VICR)
VXIbus Configuration Offset: 12 (hex)
Attributes: Read/Write 16, 8-bit accessible
15 14 13 12 11 10 9 8
0 INTEN[7] INTEN[6] INTEN[5] INTEN[4] INTEN[3] INTEN[2] INTEN[1]
76 54 321 0
0 INTDIR[7] INTDIR[6] INTDIR[5] INTDIR[4] INTDIR[3] INTDIR[2] INTDIR[1]
You can use this register to control the routing of the seven VMEbus interrupt lines
between the VXIbus and the MXIbus. Any interrupts that the VXI-MXI-2 itself generates
will be driven on the VXIbus and must be routed to the MXIbus through this register if
the handler for the interrupt is located on the MXIbus. Interrupt Acknowledge cycles are
mapped in the opposite direction of the corresponding interrupt, which allows the handler
to transparently reach the interrupter when acknowledging an interrupt. More than one
VXI-MXI-2 can route the same interrupt level to the same bus (the VXIbus or MXIbus).
This register conforms to the VXIbus Mainframe Extender specification.
Bit Mnemonic Description
15 0 Reserved
This bit is reserved. It returns 0 when read. This
bit can be written with any value.
14-8 INTEN[7:1] Interrupt Enable
Setting these bits individually enables routing of
the seven VMEbus interrupt lines between the
VXIbus and the MXIbus. Any interrupt line
whose corresponding INTEN[7:1] bit is clear is
not routed. These bits are cleared by a hard reset
and are not affected by a soft reset.
7 0 Reserved
This bit is reserved. It returns 0 when read. This
bit can be written with any value.