User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-22 © National Instruments Corporation
VXIbus TTL Trigger Configuration Register (VTCR)
VXIbus Configuration Offset: 14 (hex)
Attributes: Read/Write 16, 8-bit accessible
15 14 13 12 11 10 9 8
TTLTRGEN[7] TTLTRGEN[6] TTLTRGEN[5] TTLTRGEN[4] TTLTRGEN[3] TTLTRGEN[2] TTLTRGEN[1] TTLTRGEN[0]
76 54 321 0
TTLTRGDIR[7] TTLTRGDIR[6] TTLTRGDIR[5] TTLTRGDIR[4] TTLTRGDIR[3] TTLTRGDIR[2] TTLTRGDIR[1] TTLTRGDIR[0]
You can use this register to control the routing of the eight VXIbus TTL trigger lines
between the VXIbus and the MXIbus. Any triggers that the VXI-MXI-2 itself generates
are driven on the VXIbus and must be routed to the MXIbus through this register if the
destination for the trigger is located on the MXIbus. Likewise, the VXI-MXI-2 can sense
triggers only from the VXIbus, so any triggers originating on the MXIbus that the
VXI-MXI-2 must sense should be routed through this register to the VXIbus. More than
one VXI-MXI-2 cannot route the same trigger line to the same MXIbus. Configure only
one VXI-MXI-2 to route a trigger to a particular MXIbus at any one time. This register
conforms to the VXIbus Mainframe Extender specification.
Bit Mnemonic Description
15-8 TTLTRGEN[7:0] TTL Trigger Enable
Setting these bits individually enables routing of
the eight VXIbus TTL trigger lines between the
VXIbus and the MXIbus. Any trigger line whose
corresponding TTLTRGEN[7:0] bit is clear is
not routed. These bits are cleared by a hard reset
and are not affected by a soft reset.
7-0 TTLTRGDIR[7:0] TTL Trigger Direction
When the corresponding TTLTRGEN[7:0] bit
is clear, these bits are ignored. When the
corresponding TTLTRGEN[7:0] bit is set, these
bits control the direction in which the trigger is
routed. The trigger is routed from the VXIbus to
the MXIbus when its TTLTRGDIR[7:0] bit is 0
(outward), and from the MXIbus to the VXIbus
when its TTLTRGDIR[7:0] bit is 1 (inward).
These bits are cleared by a hard reset and are not
affected by a soft reset.