User manual

Chapter 5 Register Descriptions

VXIbus Utility Configuration Register (VUCR)

VXIbus Configuration Offset: 18 (hex)

Attributes: Read/Write 16, 8-bit accessible

15 14 13 12 11 10 9 8

TTL* ECL3* ECL2* UTIL* 1 1 1 1

76 54 321 0

1 1 ACFIN ACFOUT SFIN SFOUT SRIN SROUT

This register indicates that the VXI-MXI-2 supports TTL trigger routing and VMEbus

utility signal routing and does not support any ECL trigger routing. You can also use this

MXIbus. The VMEbus utility signals are ACFAIL*, SYSFAIL*, and SYSRESET*. Any

utility signals that the VXI-MXI-2 itself generates are driven on the VXIbus and must be

routed to the MXIbus through this register if the destination for the signal is located on

the MXIbus. Likewise, the VXI-MXI-2 can sense the three utility signals only from the

VXIbus, so any signal originating on the MXIbus that the VXI-MXI-2 must sense should

be routed through this register to the VXIbus. There are no restrictions on either the

number of VXI-MXI-2 modules routing the utility signals or the directions in which they

are routed. Also, the VXI-MXI-2 can route any utility signal in both directions

simultaneously. This register conforms to the VXIbus Mainframe Extender specification.

Bit Mnemonic Description

15 TTL* TTL Trigger Support

This read-only bit returns a 0 to indicate that the

VXI-MXI-2 supports routing of the eight

VXIbus TTL trigger lines. The value written to

this bit is irrelevant.

14 ECL3* P3 ECL Trigger Support

This read-only bit returns a 1 to indicate that the

VXI-MXI-2 does not support routing of the P3

ECL trigger lines. The value written to this bit is

irrelevant.

13 ECL2* P2 ECL Trigger Support

This read-only bit returns a 1 to indicate that the

VXI-MXI-2 does not support routing of the P2

ECL trigger lines. The value written to this bit is

irrelevant.