User manual

Chapter 5 Register Descriptions
© National Instruments Corporation 5-27 VXI-MXI-2 User Manual
VXI-MXI-2 Status Register (VMSR)
VXIbus Configuration Offset: 20 (hex)
Attributes: Read Only 16, 8-bit accessible
15 14 13 12 11 10 9 8
0 CMODE 1 POSTERR MXSCTO INTLCK DSYSFAIL FAIR
76 54 321 0
MXISC 0 0 0 SCFG MBERR 0 PARERR
This VXI-MXI-2-specific register provides status bits for various operations.
Bit Mnemonic Description
15 0 Reserved
This bit is reserved and returns 0 when read.
14 CMODE Comparison Mode Status
This bit reflects the state of the CMODE bit in
the VXI-MXI-2 Control register (VMCR).
13 1 Reserved
This bit is reserved and returns 1 when read.
12 POSTERR Write Post Error Status
This bit returns 1 when a write-posted cycle
results in an error. This is actually two bits; one
can be read from the MXIbus and the other can
be read from the VXIbus. When a VXIbus
master reads this bit as a 1, a VXIbus data cycle
that mapped to the MXIbus and was posted
results in an error. When a MXIbus master reads
this bit as a 1, a MXIbus data cycle that mapped
to the VXIbus and was posted results in an error.
Each bit clears when read and on hard and soft
resets. Write posting can be enabled using the
VXIplug&play soft front panel for the
VXI-MXI-2. Refer to Chapter 7, VXIplug&play
for the VXI-MXI-2, for more information.