User manual

Chapter 5 Register Descriptions
VXI-MXI-2 User Manual 5-28 © National Instruments Corporation
11 MXSCTO MXIbus System Controller Timeout Status
If the VXI-MXI-2 is the MXIbus System
Controller, this bit is set when the VXI-MXI-2
terminates a MXIbus cycle with a BERR due to a
bus timeout. This bit is cleared by hard and soft
resets and when read.
10 INTLCK Interlocked Status
This bit reflects the state of the INTLCK bit in
the VXI-MXI-2 Control Register (VMCR).
9 DSYSFAIL Drive SYSFAIL* Status
This bit reflects the state of the DSYSFAIL bit in
the VXI-MXI-2 Control Register (VMCR).
8 FAIR MXIbus Fair Status
This bit indicates if the VXI-MXI-2 is a fair
MXIbus requester. The VXI-MXI-2 is fair if this
bit returns a 1, and not fair if it returns a 0. Refer
to Chapter 7, VXIplug&play for the VXI-MXI-2,
or Appendix B, Programmable Configurations,
for information on configuring the VXI-MXI-2
as a fair MXIbus requester.
7 MXISC MXIbus System Controller Status
This bit returns a 1 if the VXI-MXI-2 is the
MXIbus System Controller, or a 0 when the
VXI-MXI-2 is not the MXIbus System
Controller.
6-4 0 Reserved
These bits are reserved and return 000 (binary)
when read.
3 SCFG Self-Configuration Status
After a hard reset, the VXI-MXI-2 executes an
initialization sequence called self-configuration.
When this bit returns a 1, self-configuration is in
process and the VXI-MXI-2 may not be fully
initialized. When this bit returns a 0, self-
configuration is complete and the VXI-MXI-2 is
initialized. The PASSED bit in the VXIbus
Status Register (VSR) also does not become set
until self-configuration is complete; this prevents
a Resource Manager from attempting to program
the VXI-MXI-2 before initialization is complete.