User manual

Chapter 5 Register Descriptions
© National Instruments Corporation 5-29 VXI-MXI-2 User Manual
2 MBERR MXIbus Bus Error Status
If this bit is set, the VXI-MXI-2 terminated the
previous MXIbus transfer by driving the MXIbus
BERR* line. This indicates that the cycle was
terminated because of a bus error or a retry
condition. This bit is cleared by hard and soft
resets and on successful MXIbus accesses.
1 0 Reserved
This bit is reserved and returns 0 when read.
0 PARERR Parity Error Status
If this bit is set, a MXIbus parity error occurred
on either the address or the data portion of the
last MXIbus transfer. This bit is cleared by hard
and soft resets and on MXIbus transfers without
a parity error.