User manual

Chapter 5 Register Descriptions

maps to the MXIbus, while a MXIbus cycle out

of that range maps to the VXIbus. When

HIGH[7:0] = LOW[7:0] = 0, the window is

disabled. When FF (hex) ≥ (HIGH[7:0] =

LOW[7:0]) ≥ 80 (hex), all VXIbus addresses are

mapped out to the MXIbus. When 7F (hex) ≥

(HIGH[7:0] = LOW[7:0]) > 0, all MXIbus

addresses are mapped in to the VXIbus. To

accommodate 8-bit devices that write to the

VWRx registers, the window is not enabled until

the lower byte is written. Therefore, 8-bit

masters should write the upper byte first, then the

lower byte. This bit is cleared by hard and soft

resets.

13 ECLEN[1] ECL Trigger [1] Enable

Setting this bit enables routing of the VXIbus P2

ECL trigger [1] line between the VXIbus and the

front-panel SMB connectors. If this bit is clear,

no routing is enabled between the SMB

connectors and the P2 ECL trigger [1] line. This

bit is cleared by a hard reset and is not affected

by a soft reset.

12 ECLDIR[1] ECL Trigger [1] Direction

When the ECLEN[1] bit is clear, this bit is

ignored. When the ECLEN[1] bit is set, this bit

controls the direction in which the trigger is

routed. The trigger is routed from the VXIbus to

the TRG OUT SMB connector when ECLDIR[1]

is 0 (outward), and from the TRG IN SMB

connector to the VXIbus when ECLDIR[1] is 1

(inward). This bit is cleared by a hard reset and is

not affected by a soft reset.

11 ECLEN[0] ECL Trigger [0] Enable

Setting this bit enables routing of the VXIbus P2

ECL trigger [0] line between the VXIbus and the

front-panel SMB connectors. If this bit is clear,

no routing is enabled between the SMB

connectors and the P2 ECL trigger [0] line. This

bit is cleared by a hard reset and is not affected

by a soft reset.