Datasheet
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© May 2016
Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
19/46
WPMDU1251501 / 171021501
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
Selection by load step requirements
The output voltage is also affected by load transient (see picture below).
By the output current transition from a low to a high value, the voltage at the output capacitor (V
OUT
) drops. This involves
two contributions. One is caused by the voltage drop across the ESR (V
ESR
) and depends on the slope of the rising edge
of the current step (t
rise
). For low ESR values and small load currents, this is often negligible. It can be calculated as follows:
Where
is the load step, as shown in the picture below (simplified: no voltage ripple is shown).
0 t
I
out
0 t
V
out
∆I
out
∆V
out
V
ESR
V
discharge
t
d
t
reg
t
rise
The second component is the voltage drop due to discharge of the output capacitor, which can be estimated as:
In a current mode architecture the t
d
is strictly related to the bandwidth of the regulation loop and influenced by the C
OUT
(increasing C
OUT
, the t
d
increases as well).