Datasheet
we-online.com
© May 2016
Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
27/46
WPMDU1251501 / 171021501
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
Step 8 Optional: Voltage tracking
In some applications where a digital IC with 2 or more V
CC
pins are supplied by the power modules the simultaneous
voltage rise on those pins during start up might be required (see Figure 11). Typical examples are, power supply of most
FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, V
OUT1
, usually powers the I/O, and the lower
voltage, V
OUT2
, powers the core.
This can be realized using the tracking function of the MagI³C Power Module. One module (often the higher output rail) is
set up as the master (see Figure 10, Module 1). The slave module (Module 2) has to be connected via the resistive divider
R1
TR
and R2
TR
to the output voltage rail of the primary voltage rail (V
OUT1
). The slave module output voltage is lower than
that of the master. A typical power up sequence would start at t
0
by setting the EN pin to a level above the V
EN
threshold
to turn on Module 1. After a short delay both output voltages start rising simultaneously. The lower output voltage (V
OUT2
)
reaches it’s nominal level first at time t
1
. The master module reaches it’s nominal level (V
OUT1
) later at t
2
. Proper
configuration allows the slave rail to power up coincident with the master rail such that the voltage difference between the
rails during ramp-up is small (i.e.<0.15V typ). The values for the tracking resistive divider should be selected such that the
effect of the internal 2µA current source is minimized. In most cases the ratio of the tracking divider resistors is the same
as the ratio of the output voltage setting divider. Proper operation in tracking mode dictates the soft-start time of the slave
rail to be shorter than the master rail. Therefore place an external soft-start capacitor at the master module1.
EN/UVLO
SS/TRK
INTSS
VOUT
EN/UVLO
SS/TRK
INTSS
VOUT
R
1
R
2
27
27
28
28
29
29
C
SS
AGND
AGND
V
ON
V
OUT1
V
OUT2
Figure 10. Voltage tracking configuration