Datasheet

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© May 2016
Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
29/46
WPMDU1251501 / 171021501
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
Step 9 Optional: Synchronization to an external clock
An internal phase locked loop (PLL) allows synchronization between 300 kHz and 1 MHz, and to easily switch from RT
mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with
a duty cycle between 20 % to 80 %. The clock signal amplitude must transition lower than 0.8 V and higher than 2.0 V.
The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and
CLK mode are needed, the device can be configured as shown in Figure 12.
Before the external clock is present, the device works in RT mode where the switching frequency is set by the R
RT
resistor.
When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the
RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the RT/CLK pin becomes high
impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK
mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching
frequency set by the R
RT
resistor.
RT/CLK
AGND
1 kΩ
R
RT
SSCHO
470pF
External Clock
300kHz to 1MHz
06S
29
31
Figure 12. Synchronization Configuration
Step 10 Optional: Power Good (PG)
The PG pin is an open drain output. Once the output voltage is between 94 % and 106 % of the set voltage, the PG pin
pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage
source that is 5.5 V or less. The PG pin is in a defined state once V
IN
is higher than 1.0 V, but with reduced current sinking
capability. The PG pin achieves full current sinking capability once the V
IN
pin is above 4.5 V. The PG pin is pulled low
when the output voltage is lower than 91 % or higher than 109 % of the nominal set voltage. Also, the PG pin is pulled low
if the input UVLO or thermal shutdown is asserted, the EN pin is pulled low, or the SS/TRK pin is below 1.4 V.
PG
10kΩ
V
CC
= V
IN
or other supply voltage below 5.5V
35
V
CC
AGND