Datasheet

WPMDB1400362Q / 171040302
MagI
3
C Power Module
VDRM – Variable Step Down Regulator Module
we-online.com Würth Elektronik eiSos GmbH & Co. KG – Data Sheet Rev. 1.0
© May 2016 24/48
Selection by load step requirements
The output voltage is also affected by load transients (see picture below).
When the output current transitions from a low to a high value, the voltage at the output capacitor (V
OUT
) drops. This involves
two contributing factors. One is caused by the voltage drop across the ESR (V
ESR
) and depends on the slope of the rising
edge of the current step (t
rise
). For low ESR values and small load currents, this is often negligible. It can be calculated as
follows:
V

= ESR∗∆I

(8)
Where ∆

is the load step, as shown in the picture below (simplified: no voltage ripple is shown).
0 t
I
OUT
0 t
V
OUT
∆I
OUT
∆V
OUT
V
ESR
V
discharge
t
d
t
reg
t
rise
The second contributing factor is the voltage drop due to discharge of the output capacitor, which can be estimated as:
V

=
∆I

∙t

2∙C

(9)
In a current mode architecture the t
d
is strictly related to the bandwidth of the regulation loop and influenced by the C
OUT
(increasing C
OUT
, the t
d
increases as well).