Datasheet

WPMDB1400362Q / 171040302
MagI
3
C Power Module
VDRM – Variable Step Down Regulator Module
we-online.com Würth Elektronik eiSos GmbH & Co. KG – Data Sheet Rev. 1.0
© May 2016 33/48
Step 9 Synchronizing with an external clock
An internal phase locked loop (PLL) has been implemented to allow synchronization between 500 kHz and 2 MHz, and to
easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to
the RT/CLK pin with a minimum pulse width of 75 ns. The maximum clock pulse width must be calculated using Equation 9.
The clock signal amplitude must transition lower than 0.4 V and higher than 2.2 V. The start of the switching cycle is
synchronized to the falling edge of RT/CLK pin. For applications requiring both RT mode and CLK mode, configure the
device as shown in the figure below. Before the external clock is present, the device works in RT mode and the switching
frequency is set by the RT resistor (R
RT
). When the external clock is present, the CLK mode overrides the RT mode. The
device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto
the frequency of the external clock. The device will lock to the external clock frequency approximately 15 µs after a valid
clock signal is present. It is not recommended to switch from CLK mode back to RT mode because the internal switching
frequency drops to a lower frequency before returning to the switching frequency set by the RT resistor.
Maximumclockpulsewidth=
0.75 ∗

1−
V

V


f

(12)
RT/CLK
1kΩ
470pF
EXTERNAL CLOCK
GENERATOR
7
AGND
INTRRT
5
Step 10 Power Good
The PG pin is an open drain output. Once the voltage on the SENSE+ pin is between 93% and 107% of the nominal value,
the PG pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ
to a voltage source that is 6 V or less. The PG pin is in a defined state once V
IN
is greater than 1.2 V, but with reduced
current sinking capability. The PG pin achieves full current sinking capability once the V
IN
pin is above 2.95V. The PG pin is
pulled low when the voltage on SENSE+ is lower than 91% or greater than 109% of the nominal set voltage. Also, the PG
pin is pulled low if the input UVLO or thermal shutdown is asserted, or if the ENABLE pin is pulled low.