Datasheet

WPMDB1400362Q / 171040302
MagI
3
C Power Module
VDRM – Variable Step Down Regulator Module
we-online.com Würth Elektronik eiSos GmbH & Co. KG – Data Sheet Rev. 1.0
© May 2016 7/48
ELECTRICAL SPECIFICATIONS
MIN and MAX limits are valid for the recommended ambient temperature range of -40°C to 85°C. Typical values represents
statistically the utmost probability at following conditions: V
IN
= 3.3V, V
OUT
= 1.8V, I
OUT
= 4A, C
IN1
= 47µF ceramic,
C
IN2
= 220µF polymer electrolytic, C
OUT1
= 47µF ceramic, C
OUT2
= 100µF poly-tantalum unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS MIN
(1)
TYP
(2)
MAX
(1)
UNIT
Output current
I
OCP
Over current protection - 7 - A
Accuracy
V
FB
Reference accuracy
T
A
= 25°C, I
OUT
= 0A
with internal feedback resistor
- - ±1
(7)
%
Temperature variation -40°C≤T
A
≤85°C, I
OUT
= 0A - ±0.3 - %
V
OUT
Line regulation
Over V
IN
range, T
A
= 25°C,
I
OUT
= 0A
- ±0.1 - %
Load regulation Over I
OUT
range, T
A
= 25°C - ±0.1 - %
Total output voltage variation - - ±1.5 %
Output voltage ripple 10µF ceramic, 20MHz BW
(8)
- 5 - mV
pp
Switching frequency
f
SW
Switching frequency
Using RT mode 500 - 2000 kHz
RT/CLK pin open 400 500 600 kHz
f
CLK
Synchronization clock
frequency range
Using CLK mode
500 - 2000 kHz
Minimum CLK pulse width 75 - - ns
V
CLK-H
RT/CLK high threshold
Relative to AGND
2.2 - 3.3 V
V
CLK-L
RT/CLK low threshold -0.3 - 0.4 V
f
CLK
RT/CLK to switch node delay - 90 - ns
PLL lock-in-time - 14 - µs
Enable and undervoltage lockout
V
UVLO
V
IN
undervoltage threshold
V
IN
increasing, UVLO pin
connected to AGND
- 3.05 3.135 V
V
IN
decreasing, UVLO pin
connected to AGND
2.5 2.75 - V
V
ENABLE
Enable threshold trip point
Enable logic high voltage - 1.25 - V
Enable logic low voltage -0.3 - 1.0 V
Power Good
PG
Power Good threshold
V
OUT
rising, V
OUT
GOOD - 93 - %
V
OUT
rising, V
OUT
FAULT - 107 - %
V
OUT
falling, V
OUT
GOOD - 105 - %
V
OUT
falling, V
OUT
FAULT - 91 - %
Power Good low voltage I
PG
= 0.33mA - - 0.3 V