Datasheet
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Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
12/29
WPMDH1200601 / 171020601
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
DESIGN FLOW
If the system design requires a certain maximum value of input ripple voltage ΔV
IN
to be maintained then the following
equation may be used:
(10)
If ΔV
IN
is 1% of V
IN
for a 24V input to 3.3V output application this equals 240 mV and f
SW
= 400 kHz.
Step 4. Select Output Capacitor (C
OUT
)
None of the required output capacitance is integrated within the module. At a minimum, the output capacitor must
meet the worst case RMS current rating of
, as calculated in equation (8). Beyond that, additional
capacitance will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10µF is
generally required. Please consider the derating of the nominal capacitance value dependent on the DC voltage
applied across it. Experimentation will be required if attempting to operate with a minimum value. Low ESR
capacitors, such as ceramic and polymer electrolytic capacitors are recommended.
Capacitance:
The following equation provides a good first pass approximation of C
OUT
for load transient requirements:
(11)
For example:
Solving:
ESR:
The ESR of the output capacitor affects the output voltage ripple. High ESR will result in larger V
OUT
peak-to-peak
ripple voltage. Furthermore, high output voltage ripple caused by excessive ESR can trigger the over-voltage
protection monitored at the FB pin. The ESR should be chosen to satisfy the maximum desired V
OUT
peak-to-peak
ripple voltage and to avoid over-voltage protection during normal operation. The following equations can be used:
(12)
where
(peak to peak inductor ripple current) is calculated using equation (8).
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.