Datasheet

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Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
11/25
WPMDM1500602/ 171050601
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
DESIGN FLOW
Note that the stability requirement for 200μF minimum output capacitance will take precedence.
One recommended output capacitor combination is a 220uF, 7 milliohm ESR specialty polymer cap in parallel with a
100µF 6.3V X5R ceramic. This combination provides excellent performance that may exceed the requirements of
certain applications. Additionally some small ceramic capacitors can be used for high frequency EMI suppression.
Step 4. Select Soft-Start Capacitor (C
SS
)
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled,
thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 1.6ms circuit slowly ramps the SS/TRK input
to implement internal soft start. If 2ms is an adequate turn–on time then the Css capacitor can be left unpopulated.
Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft start duration is given by the formula:








(6)
with t
ss
= select soft-start time in (ms)
Using a 0.22μF capacitor results in 3.5ms typical soft-start duration; and 0.47μF results in 7.5ms typical. 0.47μF is a
recommended initial value. As the soft-start input exceeds 0.796V the output of the power stage will be in regulation
and the 50μA current is deactivated. Note that the following conditions will reset the soft-start capacitor by
discharging the SS input to ground with an internal current sink.
 The enable input being “pulled low”
 Thermal shutdown condition
 Internal V
CC
UVLO (Approx 4.3V input to V
IN
)
Step 5. Optional: Voltage tracking
The tracking function allows the module to be connected as a slave supply to a primary voltage rail (often the 3.3V
system rail) where the slave module output voltage is lower than that of the master. Proper configuration allows the
slave rail to power up coincident with the master rail such that the voltage difference between the rails during ramp-up
is small (i.e.<0.15V typ). The values for the tracking resistive divider should be selected such that the effect of the
internal 50uA current source is minimized. In most cases the ratio of the tracking divider resistors is the same as the
ratio of the output voltage setting divider. Proper operation in tracking mode dictates the soft-start time of the slave
rail be shorter than the master rail; a condition that is easy satisfy since the C
SS
cap is replaced by R
TKB
. The tracking
function is only supported for the power up interval of the master supply; once the SS/TRK rises past 0.8V the input is
no longer enabled and the 50 µA internal current source is switched off.
SS/TRK
INT VCC
50µA
5V V
OUT
R
fbt
2.26k
R
fbb
1.07k
FB
3.3V Master
R
tkt
226k
R
tkb
107k
Figure 2. Tracking option input detail