Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 36 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
6.15.2 Register map
The addressable register space contains 128 registers with addresses from 0x00 to 0x7F.
An overview of the register mapping is provided in Table 34
to Table 42. The functionality
of individual bits is discussed in more detail in relevant sections of the data sheet.
Table 34. Overview of primary control registers
Address Register Name Bit:
7 6 5 4 3 2 1 0
0x00 Watchdog control WMC reserved NWP
0x01 Mode control reserved MC
0x03 Main status reserved OTWS NMS RSS
0x04 System event enable reserved OTWE SPIFE reserved
0x05 Watchdog status reserved FNMS SDMS WDS
0x06 Memory 0 GPM[7:0]
0x07 Memory 1 GPM[15:8]
0x08 Memory 2 GPM[23:16]
0x09 Memory 3 GPM[31:24]
0x0A Lock control reserved LK6C LK5C LK4C LK3C LK2C LK1C LK0C
Table 35. Overview of V1 and INH/VEXT and transceiver control registers
Address Register Name Bit:
7 6 5 4 3 2 1 0
0x10 V1 and INH/VEXT control reserved VEXTC V1RTC
0x1B Supply status reserved VEXTS V1S
0x1C Supply event enable reserved VEXTOE VEXTUE V1UE
0x20 CAN control reserved CMC
0x22 Transceiver status CTS reserved CBSS reserved VCS CFS
0x23 Transceiver event enable reserved CBSE reserved CFE CWE
Table 36. Overview of WAKE pin control and status registers
Address Register Name Bit:
7 6 5 4 3 2 1 0
0x4B WAKE pin status reserved WPVS reserved
0x4C WAKE pin enable reserved WPRE WPFE
Table 37. Overview of event capture registers
Address Register Name Bit:
7 6 5 4 3 2 1 0
0x60 Global event status reserved WPE TRXE SUPE SYSE
0x61 System event status reserved PO reserved OTW SPIF WDF
0x62 Supply event status reserved VEXTO VEXTU V1U
0x63 Transceiver event status reserved CBS reserved CF CW
0x64 WAKE pin event status reserved WPR WPF