Technical data

LZT 123 1834 36
5.3.1.2 I2C Level Shifter Interface
Because of the nature of the I
2
C interface signals, SDA (data) & SCL (clock), they utilize
a different type of level-shifting technology to that of the ‘common’ IO. The I
2
C level
shifter IC uses an open drain construction with no direction pin, ideally suited to bi-
directional low voltage (such as the GR64 1.8 V processor) I
2
C port translation to the
normal 3.3 V or 5.0 V I
2
C-bus signal levels. Unlike the common level shifters, the I
2
C
level shifters have a very low (6.5ohm RDS
ON
) resistance between input and output
pins.
The I
2
C level shifters use VREF as the host-side voltage reference and the internal
1.8V digital IO core as the module-side reference.