Features • MPEG I/II-Layer 3 Hardwired Decoder • • • • • • • • • • – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.
Description The AT83SND2CMP3 has been developped as a versatile remote controlled MP3 player for very fast MP3 feature implementation into most existing system. It perfectly fits features needed in mobile phones and toys, but can also be used in any portable equipment and in industrial applications. Audio files and any other data can be stored in a Nand Flash memory or in a removable Flash card such as MultiMediaCard (MMC) or Secure Digital Card (SD).
AT83SND2CMP3 Block Diagram Figure 1.
Pin Description Pinouts Figure 3. AT83SND2CMP3 100-pin BGA Package 10 9 8 7 6 5 4 3 2 1 NC NC P2.0/ A8 P4.1/ VDD VSS NC AUXP AUXN NC A VDD P2.2/ A10 P2.1/ A9 P4.0/ P4.2/ MONON MONOP P0.0/ AD0 KIN0 NC B P2.4/ A12 P2.3/ A11 P2.5/ A13 P4.3/ P0.6/ AD6 P0.4/ AD4 P0.3/ AD3 P0.2/ AD2 P0.1/ AD1 NC C P2.6/ A14 P2.7/ A15 MCLK NC P0.7/ AD7 P0.5/ AD5 NC NC NC NC D NC VSS VDD ESDVSS VDD SDA AUDVREF SCL HSL AUDVDD E MCMD MDAT NC P3.2/ INT0 P3.
AT83SND2CMP3 Signals All the AT83SND2CMP3 signals are detailed by functionality in following tables. Table 1. Ports Signal Description Signal Name Type Description P0.7:0 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. P2.7:0 I/O Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Signal Name Type Alternate Function Description Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.5 External Interrupt 1 INT1 input sets IE1 in the TCON register.
AT83SND2CMP3 Table 7. UART Signal Description Signal Name Type RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 Description Alternate Function Table 8.
Signal Name Type Description UVSS GND USB Ground Connect this pin to ground. Alternate Function - Table 11. Audio Power Signal Description Signal Name Type Description Alternate Function AUDVDD PWR Audio Digital Supply Voltage - AUDVSS GND Audio Circuit Ground Connect these pins to ground. - ESDVSS GND AUDVREF PWR Audio Voltage Reference pin for decoupling. - HSVDD PWR Headset Driver Power Supply.
AT83SND2CMP3 Internal Pin Structure Table 13. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST Input/Output RST Input/Output P3 P4 Input/Output P0 MCMD MDAT RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P N VSS ALE SCLK DCLK VDD P Output N DOUT DSEL MCLK VSS D+ Input/Output D+ D- D- Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the DC Characteristics.
Clock Controller The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller. Oscillator The X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 4) that can be configured with off-chip components such as a Pierce oscillator (see Figure 5). Value of capacitors and crystal characteristics are detailed in the section “DC Characteristics”.
AT83SND2CMP3 Fi gure 7) . Value of the filter components ar e detailed in the Section “ DC Characteristics”. The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref produced by the charge pump. It generates a square wave signal: the PLL clock. Figure 6. PLL Block Diagram and Symbol PFILT PLLCON.1 PLLEN N divider OSC CLOCK Up N6:0 PFLD CHP Vref VCO Down PLOCK PLL Clock R divider PLLCON.
MP3 Decoder The product implements a MPEG I/II audio layer 3 decoder better known as MP3 decoder. In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about 32M bytes of storage, can be encoded into only 2.
AT83SND2CMP3 MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame in its input buffer(1). In order to manage the load of MP3 data in the frame buffer, a hardware handshake consisting of data request and data acknowledgment is implemented. Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can generate an interrupt if enabled as explained in Section “Interrupt”.
Audio Controls Volume Control The MP3 decoder implements volume control on both right and left channels. The MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 15. Table 15. Volume Control Equalization Control VOL4:0 or VOR4:0 Volume Gain (dB) 00000 Mute 00001 -33 00010 -27 11110 -1.5 11111 0 Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium band from 750 Hz to 3300 Hz and a treble band over 3300 Hz.
AT83SND2CMP3 Frame Information The MP3 frame header contains information on the audio data contained in the frame. These informations is made available in the MP3STA register for you information. MPVER and MPFS1:0 bits allow decoding of the sampling frequency according to Table 17. MPVER bit gives the MPEG version (2 or 1). Table 17. MP3 Frame Frequency Sampling Ancillary Data MPVER MPFS1 MPFS0 Fs (kHz) 0 0 0 22.
Audio Output Interface The product implements an audio output interface allowing the audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and thanks to the on-chip PLL (see Section “Clock Controller”, page 10) allows connection of almost all of the commercial audio DAC families available on the market. The audio bitstream can be from 2 different types: Description • The MP3 decoded bitstream coming from the MP3 decoder for playing songs.
AT83SND2CMP3 Clock Generator The audio interface clock is generated by division of the PLL clock. The division factor is given by AUCD4:0 bits in CLKAUD register. Figure 14 shows the audio interface clock generator and its calculation formula. The audio interface clock frequency depends on the incoming MP3 frames and the audio DAC used. Figure 14.
Figure 16. Audio Output Format DSEL DCLK DOUT Left Channel 1 2 3 Right Channel 13 14 15 LSB MSB B14 16 B1 1 2 3 13 14 15 LSB MSB B14 16 B1 I2S Format with DSIZ = 0 and JUST4:0 = 00001. DSEL DCLK Left Channel 1 DOUT 2 Right Channel 3 17 MSB B14 LSB 18 32 1 2 3 17 MSB B14 LSB 18 32 I2S Format with DSIZ = 1 and JUST4:0 = 00001.
AT83SND2CMP3 Table 18. Sample Duplication Factor DUP1 DUP0 Factor 0 0 No sample duplication, DAC rate = 8 kHz (C51 rate). 0 1 One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 1 0 2 samples duplication, DAC rate = 32 kHz (4 x C51 rate). 1 1 Three samples duplication, DAC rate = 48 kHz (6 x C51 rate). MP3 Buffer In song playing mode, the audio stream comes from the MP3 decoder through a buffer.
Figure 18.
AT83SND2CMP3 DAC and PA Interface The AT83SND2CMP3 implements a stereo Audio Digital-to-Analog Converter and Audio Power Amplifier targeted for Li-Ion or Ni-Mh battery powered devices. Figure 19.
DAC Features • 20 bit D/A Conversion • 72dB Dynamic Range, -75dB THD Stereo line-in or microphone interface with 20dB • • • • • • amplification 93dB Dynamic Range, -80dB THD Stereo D/A conversion 74dB Dynamic Range / -65dB THD for 20mW output power over 32 Ohm loads Stereo, Mono and Reverse Stereo Mixer Left/Right speaker short-circuit detection flag Differential mono auxiliary input amplifier and PA driver Audio sampling rates (Fs): 16, 22.05, 24, 32, 44.1 and 48 kHz. Figure 20.
AT83SND2CMP3 Figure 21. 20 bit I2S justified mode SCLK DSEL DOUT R1 R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 L(N-1) ... L1 L0 Figure 22. 20 bit MSB justified mode SCLK DSEL DOUT R0 L(N-1) L(N-2) Figure 23. 20 bit LSB justified mode SCLK DSEL DOUT R0 L(N-1) L(N-2) R(N-1) R(N-2) ...
Audio DAC Serial Audio Interface Figure 24. Serial Audio Interface AUDCDIN AUDCDOUT AUDCCLK AUDCCS Audio PA Protocol is as following to access DAC registers: Figure 25. Dac SPI Interface AUDCCS AUDCCLK rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 AUDCDIN AUDCDOUT DAC Interface SPI Protocol d7 d6 d5 d4 d3 d2 d1 d0 On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a read operation.
AT83SND2CMP3 CLK. Falling edge latches AUDCDIN input and rising edge shifts AUDCDOUT output bits. Note that the DLCK must run during any DAC SPI interface access (read or write). Figure 26. DAC SPI Interface Timings AUDCCS Tc Tssen Thsen Twl AUDCCLK Twh Tssdi Thsdi AUDCDIN Tdsdo Thsdo AUDCDOUT Table 19.
DAC Register Tables DAC Gain Table 20.
AT83SND2CMP3 Table 21. Line-in gain (Continued) 01101 -24 01110 -27 01111 -30 10000 -33 10001 < -60 Table 22. Master Playback Gain LMPG 5:0 RMPG 5:0 Gain (dB) 000000 12.0 000001 10.5 000010 9.0 000011 7.5 000100 6.0 000101 4.5 000110 3.0 000111 1.5 001000 0.0 001001 -1.5 001010 -3.0 001011 -4.5 001100 -6.0 001101 -7.5 001110 -9.0 001111 -10.5 010000 -12.0 010001 -13.5 010010 -15.0 010011 -16.5 010100 -18.0 010101 -19.5 010110 -21.0 010111 -22.
Table 22. Master Playback Gain (Continued) LMPG 5:0 RMPG 5:0 Gain (dB) 011010 -27.0 011011 -28.5 011100 -30.0 011101 -31.5 011110 -33.0 011111 -34.5 100000 mute Table 23. Line-out Gain LLOG 5:0 28 RLOG 5:0 Gain (dB) 000000 0.0 000001 -1.5 000010 -3.0 000011 -4.5 000100 -6.0 000101 -7.5 000110 -9.0 000111 -10.5 001000 -12.0 001001 -13.5 001010 -15.0 001011 -16.5 001100 -18.0 001101 -19.5 001110 -21.0 001111 -22.5 010000 -24.0 010001 -25.5 010010 -27.
AT83SND2CMP3 Table 23. Line-out Gain (Continued) 010111 -34.5 011000 -36.0 011001 -37.5 011010 -39.0 011011 -40.5 011100 -42.0 011101 -43.5 011110 -45.0 011111 -46.5 100000 mute Table 24. DAC Output Level Control LOLC 2:0 Digital Mixer Control ROLC 2:0 Gain (dB) 000 6 001 3 010 0 011 -3 100 -6 The Audio DAC features a digital mixer that allows the mixing and selection of multiple input sources.
Signal Description LMSMIN1 Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable LMSMIN2 Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to disable RMSMIN1 Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable RMSMIN2 Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to disable Note: Master Clock and Sampling Frequency Selection Refer to DAC_MC register Table 38.
AT83SND2CMP3 Table 28.
Register Table 29. AUXCON Register AUXCON (S:90h) – Auxiliary Control Register 7 6 5 4 3 2 1 0 SDA SCL - AUDCDOUT AUDCDIN AUDCCLK AUDCCS KIN0 Bit Number Bit Mnemonic 7 SDA Description TWI Serial Data SDA is the bidirectional Two Wire data line. TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller.
AT83SND2CMP3 Table 30. Dac Control Register Register - DAC_CTRL (00h) 7 6 5 4 3 2 1 0 ONPADRV ONAUXIN ONDACR ONDACL ONLNOR ONLNOL ONLNIR ONLNIL Bit Bit Number Mnemonic 7 ONPADRV 6 ONAUXIN 5 ONDACR 4 ONDACL 3 ONLNOR 2 ONLNOL 1 ONLNIR 0 ONLNIL Description Differential mono PA driver Clear to power down. Set to power up. Differential mono auxiliary input amplifier Clear to power down. Set to power up. Right channel DAC Clear to power down. Set to power up.
Table 32. DAC Right Line In Gain Register - DAC_RLIG (02h) 7 6 5 4 3 2 1 0 - - - RLIG4 RLIG3 RLIG2 RLIG1 RLIG0 Bit Number Description Bit Mnemonic 7:5 - Not used 4:0 RLIG 4:0 Right channel line in analog gain selector Reset Value = 0000101b Table 33.
AT83SND2CMP3 Table 36. DAC Rigth Line Out Gain Register - DAC_RLOG (06h) 7 6 5 4 3 2 1 0 - - RLOG5 RLOG4 RLOG3 RLOG2 RLOG1 RLOG0 Bit Number Description Bit Mnemonic 7:6 - 5:0 Not used RLOG 5:0 Right channel line out digital gain selector Reset Value = 00000000b Table 37.
Table 38. Dac Mixer Control Register - DAC_MC (08h) 7 6 5 4 3 2 1 0 - - INVR INVL RMSMIN2 RMSMIN1 LMSMIN2 LMSMIN1 Bit Bit Mnemonic Number 7:6 - 5 INVR 4 INVL 3 RMSMIN2 2 RMSMIN1 1 LMSMIN2 0 LMSMIN1 Description Not used Right channel mixer output invert Set to enable. Clear to disable. Left channel mixer output invert. Set to enable. Clear to disable. Right Channel Mono/Stereo Mixer Right Mixed input enable Set to enable. Clear to disable.
AT83SND2CMP3 Table 40. Dac Miscellaneous Register - DAC_ MISC (0Ah) 7 6 5 4 3 2 1 0 - - DINTSEL1 DINTSEL0 DITHEN DEEMPEN NBITS1 NBITS0 Bit Bit Mnemonic Number Description 7 - Not used 6 - Not used DINTSEL1:0 I2S data format selector 3 DITHEN Dither enable (Clear this bit to disable, set to enable) 2 DEEMPEN De-emphasis enable (clear this bit to disable, set to enable) 1:0 NBITS 1:0 Data interface word length 5:4 Reset Value = 00000010b Table 41.
Table 42. DAC Auxilary input gain Register - DAC_ AUXG (0Dh)l 7 6 5 4 3 2 1 0 - - - AUXG4 AUXG3 AUXG2 AUXG1 AUXG0 Bit Number Bit Mnemonic 7:5 - 4:0 AUXG 4:0 Description Not used Differential mono auxiliary input analog gain selector Reset Value = 0000101b DAC Reset Register - DAC_ RST (10h) 7 6 5 4 3 2 1 0 - - - - - RESMASK RESFILZ RSTZ Bit Number Bit Mnemonic 7:3 - 2 RESMASK 1 RESFILZ 0 RSTZ Description Not Used.
AT83SND2CMP3 Power Amplifier High quality mono output is provided. The DAC output is connected through a buffer stage to the input of the Audio Power Amplifier, using two coupling capacitors The mono buffer stage also includes a mixer of the LINEL and LINER inputs as well as a differential monaural auxiliary input (line level) which can be, for example, the output of a voice CODEC output driver in mobile phones.
Table 44. PA Operating Mode APAON APAPRECH Operating Mode 0 0 Stand-By 0 1 Input Capacitors Precharge 1 0 Active Mode 1 1 Forbidden State Table 45. PA Low Power Mode APALP Audio Supplies and Start-up Power Mode 0 Low power mode 1 High power mode In operating mode AUDVBAT (supply of the audio power amplifier) must be between 3V and 5,5V. AUDVDD, HSVDD and VDD must be inferior or equal to AUDVBAT.
AT83SND2CMP3 Example Start I2S Example Stop I2S: • Start DCLK. • RSTMASK=1. • RESFILZ=0 and RSTZ=0. • RESFILZ=1 and RSTZ=1. • RSTMASK=0. • Delay 5 ms. • ONDACL=1 and ONDACR=1. • Program all DAC settings: audio format, gains... • DAC off: ONDACL=0 and ONDACR=0. • Stop I2S and DLCK. Audio PA Sequence PA Power-On Sequence To avoid an audible ‘click’ at start-up, the input capacitors have to be pre-charged before the Power Amplifier.
Register Table 47.
AT83SND2CMP3 Universal Serial Bus The product implements a USB device controller supporting full speed data transfer.
Description The USB device controller provides the hardware that the AT83SND2CMP3 needs to interface a USB link to a data flow stored in a double port memory. It requires a 48 MHz reference clock provided by the clock controller as detailed in Section "", page 44. This clock is used to generate a 12 MHz Full Speed bit clock from the received USB differential data flow and to transmit data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block.
AT83SND2CMP3 Clock Controller The USB controller clock is generated by division of the PLL clock. The division factor is given by USBCD1:0 bits in USBCLK register. Figure 30 shows the USB controller clock generator and its calculation formula. The USB controller clock frequency must always be 48 MHz. Figure 30.
Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and unstuffing. • CRC generation and checking. • ACKs and NACKs automatic generation. • TOKEN type identifying. • Address checking. • Clock recovery (using DPLL). Figure 31.
AT83SND2CMP3 Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT83SND2CMP3 and the SIE. It manages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Figure 33 shows typical USB IN and OUT transactions reporting the split in the hardware (UFI) and software (C51) load. Figure 32.
Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake-up purpose. When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value should be 0 in the other cases.
AT83SND2CMP3 USB Interrupt System Interrupt System Priorities D+ D- Figure 35. USB Interrupt Control System 00 01 10 11 USB Controller EUSB EA IE1.6 IE0.7 IPH/L Priority Enable Interrupt Enable Lowest Priority Interrupts Table 1. Priority Levels USB Interrupt Control System IPHUSB IPLUSB USB Priority Level 0 0 0..................Lowest 0 1 1 1 0 2 1 1 3..................Highest As shown in Figure 36, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data.
Figure 36. USB Interrupt Control Block Diagram Endpoint X (X = 0..2) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 EPXINT UEPSTAX.6 UEPINT.X RXSETUP EPXIE UEPSTAX.2 UEPIEN.X STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU EUSB USBINT.5 EWUPCPU IE1.6 USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.
AT83SND2CMP3 MultiMedia Card Controller The AT83SND2CMP3 implements a MultiMedia Card (MMC) controller. The MMC is used to store MP3 encoded audio files in removable Flash memory cards that can be easily plugged or removed from the application. Card Concept The basic MultiMedia Card concept is based on transferring data via a minimum number of signals.
Bus Lines The MultiMedia Card bus architecture requires all cards to be connected to the same set of lines. No card has an individual connection to the host or other devices, which reduces the connection costs of the MultiMedia Card system. The bus lines can be divided into three groups: Bus Protocol • Power supply: VSS1 and VSS2, VDD – used to supply the cards. • Data transfer: MCMD, MDAT – used for bi-directional communication. • Clock: MCLK – used to synchronize data transfer across the bus.
AT83SND2CMP3 Figure 38. (Multiple) Block Read Operation Stop Command MCMD Command Response MDAT Command Response Data Block CRC Data Block CRC Data Block CRC Block Read Operation Data Stop Operation Multiple Block Read Operation As shown in Figure 39 and Figure 40 the data write operation uses a simple busy signalling of the write operation duration on the data line (MDAT). Figure 39.
Table 48. Command Token Format Bit Position 47 46 45:40 39:8 7:1 0 Width (Bits) 1 1 6 32 7 1 Value ‘0’ ‘1’ - - - ‘1’ Start bit Transmission bit Command Index Argument CRC7 End bit Description Response Token Format There are five types of response tokens (R1 to R5). As shown in Figure 43, responses have a code length of 48 bits or 136 bits. A response token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit: a high level on MCMD line.
AT83SND2CMP3 Table 51. R3 Response Format (OCR Register) Bit Position 47 46 [45:40] [39:8] [7:1] 0 Width (bits) 1 1 6 32 7 1 Value ‘0’ ‘0’ ‘111111’ - ‘1111111’ ‘1’ Start bit Transmission bit Reserved OCR register Reserved End bit Description Table 52.
required, to provide 8 (eight) clock cycles for the card to complete the operation before shutting down the clock. Following is a list of the various bus transactions: Description • A command with no response. 8 clocks after the host command End bit. • A command with response. 8 clocks after the card command End bit. • A read data transaction. 8 clocks after the End bit of the last data block. • A write data transaction. 8 clocks after the CRC status token.
AT83SND2CMP3 Figure 46. MMC Clock Generator and Symbol OSC CLOCK Controller Clock OSCclk MMCclk = ----------------------------MMCD + 1 MMCLK MMCEN MMCON2.7 MMCD7:0 MMC Clock MMC CLOCK MMC Clock Symbol As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system clock. The MMC command and data clock is generated on MCLK output and sent to the command line and data line controllers. Figure 47 shows the MMC controller configuration flow.
Command Line Controller As shown in Figure 48, the command line controller is divided in 2 channels: the command transmitter channel that handles the command transmission to the card through the MCMD line and the command receiver channel that handles the response reception from the card through the MCMD line. These channels are detailed in the following sections. Figure 48. Command Line Controller Block Diagram TX Pointer 5-Byte FIFO CTPTR MMCMD Write MMCON0.
AT83SND2CMP3 User may abort command loading by setting and clearing the CTPTR bit in MMCON0 register which resets the write pointer to the transmit FIFO. Figure 49. Command Transmission Flow Command Transmission Configure Response RESPEN = X RFMT = X CRCDIS = X Load Command in Buffer MMCMD = index MMCMD = argument Transmit Command CMDEN = 1 CMDEN = 0 Command Receiver The end of the response reception is signalled to you by the EORI flag in MMINT register.
Data Line Controller The data line controller is based on a 16-Byte FIFO used both by the data transmitter channel and by the data receiver channel. Figure 50. Data Line Controller Block Diagram MMINT.0 MMINT.2 MMSTA.3 MMSTA.4 F1EI F1FI DATFS CRC16S CRC16 and Format Checker Data Converter Serial -> // 8-Byte TX Pointer FIFO 1 DTPTR MMCON0.6 RX Pointer DRPTR MMCON0.7 16-Byte FIFO MMDAT MCBI CBUSY MMINT.1 MMSTA.5 MDAT Data Converter // -> Serial CRC16 Generator 8-Byte MMINT.
AT83SND2CMP3 Figure 51. Data Controller Configuration Flows Data Stream Configuration Data Single Block Configuration Data Multi-Block Configuration Configure Format DFMT = 0 Configure Format DFMT = 1 MBLOCK = 0 BLEN3:0 = XXXXb Configure Format DFMT = 1 MBLOCK = 1 BLEN3:0 = XXXXb Data Transmitter Configuration For transmitting data to the card user must first configure the data controller in transmission mode by setting the DATDIR bit in MMCON1 register.
Figure 52.
AT83SND2CMP3 Figure 53.
This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4). Data is read from the FIFO by reading to MMDAT register. Each time one FIFO becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data. Data Reading Figure 54.
AT83SND2CMP3 Figure 55. Data Block Reception Flows Data Block Reception Data Block Initialization Data Block Reception ISR Start Transmission DATEN = 1 DATEN = 0 Unmask FIFOs Full F1FM = 0 F2FM = 0 FIFO Full? F1EI or F2EI = 1? FIFO Full? F1EI or F2EI = 1? Start Transmission DATEN = 1 DATEN = 0 FIFO Reading read 8 data from MMDAT No More Data To Receive? FIFO Reading read 8 data from MMDAT Mask FIFOs Full F1FM = 1 F2FM = 1 No More Data To Receive? a. Polling mode Flow Control b.
Interrupt Description As shown in Figure 56, the MMC controller implements eight interrupt sources reported in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags are detailed in the previous sections. All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM, and F2EM mask bits respectively in MMMSK register.
AT83SND2CMP3 Serial I/O Port The serial I/O port in the AT83SND2CMP3 provides both synchronous and asynchronous communication modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition.
Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the overflow of the timer. As shown in Figure 58 the Internal Baud Rate Generator is an 8-bit auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6 depending on the SPD bit in BDRCON register. The Internal Baud Rate Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON register allows doubling of the generated baud rate. Figure 58.
AT83SND2CMP3 Figure 60. Transmission Waveforms (Mode 0) TXD Write to SBUF RXD D0 D1 D2 D3 D4 D5 D6 D7 TI Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 61, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register.
Asynchronous Modes (Modes 1, 2 and 3) The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 64 shows the Serial Port block diagram in such asynchronous modes. Figure 64. Serial I/O Port Block Diagram (Modes 1, 2 and 3) SCON.6 SCON.7 SCON.3 SM1 SM0 TB8 Mode Decoder SBUF Tx SR TXD Rx SR RXD M3 M2 M1 M0 T1 CLOCK Mode & Clock Controller IBRG CLOCK SBUF Rx PER CLOCK SM2 TI RI SCON.4 SCON.1 SCON.0 RB8 SCON.2 Mode 1 is a full-duplex, asynchronous mode.
AT83SND2CMP3 Framing Error Detection (Modes 1, 2 and 3) Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 67. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by 2 devices.
Table 56. Internal Baud Rate Generator Value FPER = 6 MHz(1) FPER = 8 MHz(1) FPER = 10 MHz(1) Baud Rate SPD SMOD1 BRL Error % SPD SMOD1 BRL Error % SPD SMOD1 BRL Error % 115200 - - - - - - - - - - - - 57600 - - - - 1 1 247 3.55 1 1 245 1.36 38400 1 1 246 2.34 1 1 243 0.16 1 1 240 1.73 19200 1 1 236 2.34 1 1 230 0.16 1 1 223 1.36 9600 1 1 217 0.16 1 1 204 0.16 1 1 191 0.16 4800 1 1 178 0.16 1 1 152 0.16 1 1 126 0.
AT83SND2CMP3 Figure 71. Baud Rate Formula (Mode 2) Baud_Rate= Multiprocessor Communication (Modes 2 and 3) 2SMOD1 ⋅ FPER 32 Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable this feature, set SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set).
The following is an example of how to use given addresses to address different slaves: Slave A:SADDR = 1111 0001b SADEN = 1111 1010b Given = 1111 0X0Xb Slave B:SADDR = 1111 0011b SADEN = 1111 1001b Given = 1111 0XX1b Slave C:SADDR = 1111 0011b SADEN = 1111 1101b Given = 1111 00X1b The SADEN Byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.
AT83SND2CMP3 Interrupt The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 72 these flags are combined together to appear as a single interrupt source for the C51 core. Flags must be cleared by software when executing the serial interrupt service routine. The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Keyboard Interface The AT83SND2CMP3 implement a keyboard interface allowing the connection of a keypad. It is based on one input with programmable interrupt capability on both high or low level. This input allows exit from idle and power down modes. Description The keyboard interfaces with the C51 core through 2 special function registers: KBCON, the keyboard control register; and KBSTA, the keyboard control and status register.
AT83SND2CMP3 Electrical Characteristics Absolute Maximum Rating Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS .................................... -0.3 *NOTICE: to +4.0 V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
Table 57. Digital DC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Typ(1) Min Max Units VDD < 3.3 V AT83SND2CMP3 Operating Current X1 / X2 mode 7/ 11.5 9/ 14.5 10.5 / 18 IDL AT83SND2CMP3 Idle Mode Current X1 / X2 mode 6.3 / 9.1 7.4 / 11.3 8.5 / 14 mA IPD AT83SND2CMP3 Power-Down Mode Current 500 µA IDD 20 Notes: Test Conditions mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V 12 MHz 16 MHz 20 MHz VRET < VDD < 3.3 V 1. Typical values are obtained using VDD= 3 V and TA= 25°C.
AT83SND2CMP3 Figure 77. IDL Test Condition, Idle Mode VDD VDD PVDD UVDD AUDVDD RST VSS (NC) Clock Signal X2 X1 IDL VDD P0 VSS PVSS UVSS AUDVSS VSS TST All other pins are unconnected Figure 78. IPD Test Condition, Power-Down Mode VDD VDD PVDD UVDD AUDVDD RST VSS (NC) X2 X1 VDD P0 MCMD VSS PVSS UVSS AUDVSS VSS IPD MDAT TST All other pins are unconnected Oscillator & Crystal Schematic Figure 79.
VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Min Typ Max Unit CX1 Internal Capacitance (X1 - VSS) 10 pF CX2 Internal Capacitance (X2 - VSS) 10 pF CL Equivalent Load Capacitance (X1 - X2) 5 pF DL Drive Level 50 µW Crystal Frequency 20 MHz RS Crystal Series Resistance 40 Ω CS Crystal Shunt Capacitance 6 pF Max Unit F Phase Lock Loop Schematic Figure 80. PLL Filter Connection FILT R C2 C1 VSS Parameters VSS Table 60. PLL Filter Characteristics VDD = 2.7 to 3.
AT83SND2CMP3 DAC and PA Electrical Specifications AUDVBAT = 3.6V, TA = 25°C unless otherwise noted. PA High power mode, 100nF capacitor connected between CBP and AUDVSS, 470nF input capacitors, Load = 8 ohms. Figure 82. PA Specification Symbol AUDVBAT IDD Parameter Conditions Supply Voltage Min Typ Max Unit 3.2 - 5.
600 Dissipated Power [mW] 550 500 450 8 Ohms load 400 6.5 Ohms load 350 300 250 200 3,2 3,4 3,6 3,8 4 Supply Voltage AUDVBAT [V] 4,2 Figure 84. Dissipated Power vs Output Power, AUDVBAT = 3.2V 600 550 Dissipated Power [mW] 500 450 400 350 8 Ohms load 300 6.5 Ohms load 250 200 150 100 50 0 0 100 200 300 400 500 600 700 800 Output Power [mW] DAC AUDVDD, HSVDD = 2.8 V, Ta=25°C, typical case, unless otherwise noted All noise and distortion specifications are measured in the 20 Hz to 0.
AT83SND2CMP3 OVERALL MIN TYP MAX UNITS Digital Supply Voltage (VDD) 2.4 2.8 3.3 V Audio Amplifier Supply (AUDVBAT) 3.2 - 5.5 V DIGITAL INPUTS/OUTPUTS Resolution 20 Bits Logic Family CMOS Logic Coding 2’s Complement ANALOG PERFORMANCE – DAC to Line-out/Headphone Output Output level for full scale input (for AUDVDD, HSVDD = 2.8 V) Output common mode voltage 1.65 Vpp 0.
OVERALL MIN Input level for full scale output - 0dBFS Level @ AUDVDD, HSVDD = 2.8 V and 0 dB gain @ AUDVDD, HSVDD = 2.8 V and 20 dB gain Input common mode voltage Input impedance 7 TYP MAX UNITS 1.65 Vpp 583 mVrms 0.165 Vpp 58.3 mVrms 0.
AT83SND2CMP3 OVERALL MIN TYP MAX UNITS DIGITAL FILTER PERFORMANCE Frequency response (10 Hz to 20 kHz) +/- 0.1 dB Deviation from linear phase (10 Hz to 20 kHz) +/- 0.1 deg Passband 0.1 dB corner 0.4535 Fs Stopband 0.5465 Fs Stopband Attenuation 65 dB DE-EMPHASIS FILTER PERFORMANCE (for 44.1kHz Fs) Frequency Gain Pass band 0Hz to 3180Hz Transition band 3180Hz to 10600Hz Stop Band 10600Hz to 20kHz -1dB Logarithm decay -10.
Digital Filters Transfer Function Figure 86. Channel Filter Figure 87.
AT83SND2CMP3 Figure 88. DAC and PA Connection Audio DAC and PA Connection PAINN Battery AUDVSS 3.2V to 5.
Table 62.
AT83SND2CMP3 MMC Interface Definition of symbols Table 63. MMC Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Table 64. MMC Interface AC timings VDD = 2.7 to 3.
Audio Interface Definition of symbols Table 65. Audio Interface Timing Symbol Definitions Signals Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Table 66. Audio Interface AC timings Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL≤ 30pF Symbol Min Max Unit 325.
AT83SND2CMP3 External Clock Drive and Logic Level References Definition of symbols Table 67. External Clock Timing Symbol Definitions Signals C Timings Conditions Clock H High L Low X No Longer Valid Table 68. External Clock AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol Parameter Max Unit TCLCL Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns Cyclic Ratio in X2 mode 40 TCR Waveforms Min 60 % Figure 91.
Note: 92 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH= ±20 mA.
AT83SND2CMP3 Ordering Information Table Possible order entries Part Number AT83SND2MP3A17FTUL Supply Voltage 3V Temperature Range Industrial & Green Max Frequency Package Packing Product Marking 40 MHz BGA100 Tray 83C51SND2CMP 3A1-ULA RoHS Compliant Firmware Version Yes 2.
Package Information CTBGA100 94 AT83SND2CMP3 7524D–MP3–07/07
AT83SND2CMP3 Document Revision History Changes from 7524A07/05 to 7524B-05/06 1. Added AT83SND2CDVX part number. Changes from 7524B05/06 to 7524C - 06/07 1. Added AT83SND2CMP3A1 part number. Changes from7524C 06/07 to 7524D - 07/07 1. Updated Package drawing, CTBGA100.
Table of Contents Features ................................................................................................. 1 Typical Applications ............................................................................. 1 Description ............................................................................................ 2 Block Diagram....................................................................................... 3 Pin Description .........................................................
AT83SND2CMP3 Card Concept...................................................................................................... 51 Bus Concept ....................................................................................................... 51 Description.......................................................................................................... 56 Clock Generator.................................................................................................. 56 Command Line Controller.
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