Specifications

10
AT83SND2CMP3
7524D–MP3–07/07
Clock Controller The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock
Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this
controller.
Oscillator The X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see
Figure 4) that can be configured with off-chip components such as a Pierce oscillator
(see Figure 5). Value of capacitors and crystal characteristics are detailed in the section
“DC Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU
core, and a clock for the peripherals as shown in Figure 4. These clocks are either
enabled or disabled, depending on the power reduction mode as detailed in the section.
The peripheral clock is used to generate the Timer 0, Timer 1, MMC, SPI, and Port sam-
pling clocks.
Figure 4. Oscillator Block Diagram and Symbol
Figure 5. Crystal Connection
PLL
PLL Description The PLL is used to generate internal high frequency clock (the PLL Clock) synchronized
with an external low-frequency (the Oscillator Clock). The PLL clock provides the MP3
decoder, the audio interface, and the USB interface clocks. Figure 6 shows the internal
structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PFILT pin (see
X1
X2
PD
PCON.1
IDL
PCON.0
Peripheral
CPU Core
0
1
X2
CKCON.0
÷ 2
PER
CLOCK
Clock
Clock
Peripheral Clock Symbol
CPU
CLOCK
CPU Core Clock Symbol
OSC
CLOCK
Oscillator Clock Symbol
Oscillator
Clock
VSS
X1
X2
Q
C1
C2