Specifications

AT83SND2CMP3

7524D–MP3–07/07

Example Start I2S • Start DCLK.

• RSTMASK=1.

• RESFILZ=0 and RSTZ=0.

• RESFILZ=1 and RSTZ=1.

• RSTMASK=0.

• Delay 5 ms.

• ONDACL=1 and ONDACR=1.

• Program all DAC settings: audio format, gains...

Example Stop I2S: • DAC off: ONDACL=0 and ONDACR=0.

• Stop I2S and DLCK.

Audio PA Sequence

PA Power-On Sequence To avoid an audible ‘click’ at start-up, the input capacitors have to be pre-charged

before the Power Amplifier.

PA Power-Off Sequence To avoid an audible ‘click’ at power-off, the gain should be set to the minimum gain (-

22dB) before setting the Power Amplifier.

Precharge Control The power up of the circuit can be performed independently for several blocks. The

sequence flow starts by setting to High the block specific fastcharge control bit and sub-

sequently the associated power control bit. Once the power control bit is set to High, the

fast charging starts. This action begins a user controlled fastcharge cycle. When the

fastcharge period is over, the user must reset the associated fastcharge bit and the

block is ready for use. If a power control bit is cleared a new power up sequence is

needed.

The several blocks with independent power control are identified in Table 46. The table

describes the power on control and fastcharge bits for each block.

Table 46. Precharge and Power Control

Note: Note that all block can be precharged simultaneously.

Powered up block Power on control bit Precharge Control Bit

Vref & Vcm generator ONMSTR

PRCHARGE

(reg 12; bit 1)

Left line in amplifier ONLNIL PRCHARGELNIL

Right line in amplifier ONLNIR PRCHARGELNIR

Left line out amplifier ONLNOL PRCHARGELNOL

Right line out amplifier ONLNOR PRCHARGELNOR

Left D-to-A converter ONDACL Not needed

Right D-to-A converter ONDACR Not needed

Auxiliary input amplifier ONAUXIN PRCHARGEAUXIN

PA Driver output ONPADRV PRCHARGEPADRV