Specifications

81
AT83SND2CMP3
7524D–MP3–07/07
DAC and PA
Electrical Specifications
PA AUDVBAT = 3.6V, TA = 25°C unless otherwise noted.
High power mode, 100nF capacitor connected between CBP and AUDVSS, 470nF input
capacitors, Load = 8 ohms.
Figure 82. PA Specification
Figure 83. Maximum Dissipated Power Versus Power Supply
Symbol Parameter Conditions Min Typ Max Unit
AUDVBAT Supply Voltage 3.2 - 5.5 V
I
DD
Quiescent Current Inputs shorted, no load - 6 8 mA
I
DDstby
Standby Current Capacitance - - 2 µA
V
CBP
DC Reference - AUDVBAT/2 - V
VOS Output differential offset full gain -20 0 20 mV
Z
IN
Input impedance Active state 12K 20k 30k W
Z
LFP
Output load Full Power mode 6 8 32 W
Z
LLP
Output load Low-Power mode 100 150 300 W
C
L
Capacitive load - - 100 pF
PSRR Power supply rejection ratio
200 – 2kHz
Differential output
- 60 - dB
BW Output Frequency bandwidth
1KHz reference frequency
3dB attenuation.
470nF input coupling capacitors
50 - 20000 Hz
t
UP
Output setup time
Off to on mode. Voltage already settled.
Input capacitors precharged
- - 10 ms
V
N
Output noise Max gain, A weighted - 120 500 µV
RMS
THD
HP
Output distortion
High power mode, V
DD
= 3.2V, 1KHz,
Pout=100mW, gain=0dB
- 50 - dB
THD
LP
Output distortion
Low power mode, VDD = 3.2V , 1KHz,
Vout= 100mVpp, Max gain, load 8 ohms in
serie with 200 ohms
- 1 - %
G
ACC
Overall Gain accuracy -2 0 2 dB
G
STEP
Gain Step Accuracy -0.7 0 0.7 dB