PN532/C1 Near Field Communication (NFC) controller Rev. 3.6 — 28 November 2017 115436 Product data sheet COMPANY PUBLIC 1. General description The PN532 is a highly integrated transceiver module for contactless communication at 13.56 MHz based on the 80C51 microcontroller core.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller The PN532 supports the following host interfaces: • SPI • I2C • High Speed UART (HSU) An embedded low-dropout voltage regulator allows the device to be connected directly to a battery. In addition, a power switch is included to supply power to a secure IC. PN532_C1 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.6 — 28 November 2017 115436 © NXP B.V. 2017.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 2.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 3. Applications Mobile and portable devices Consumer applications 4. Quick reference data Table 1. Quick reference data Symbol Parameter VBAT Product data sheet COMPANY PUBLIC battery supply voltage [1] Min Typ Max Unit 2.7 - 5.5 V 2.7 3 3.4 V - 3.6 V ICVDD LDO output voltage VBAT > 3.4 V VSS = 0 V PVDD Supply voltage for host interface VSS = 0 V 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 5. Ordering information Table 2. Ordering information Type number Package Name PN5321A3HN/C1xx[1][2][4] [1] PN532_C1 Product data sheet COMPANY PUBLIC Description Version HVQFN40 Heatsink Very thin Quad Flat package; 40 pins, plastic, body 6 x 6 x 0.85 mm; leadless; MSL level 2[3]. SOT618-1 xx refers to the ROM code version. The ROM code functionalities are described in the User-Manual document.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 6. Block diagram VBAT P35 I0 I1 LoadMod DVDD SVDD SIGIN Power Distribution 80C51 P34 ROM RAM Host TX1 interfaces Contactless Interface Unit TX2 IRQ P30 P31 P32 P33 (PCR) RAM (CIU) PVDD NSS MOSI MISO SCK SIGOUT Power Clock Reset controller TVDD RSTOUT_N RSTPD_N PN532 Oscin Oscout AVDD RX VMID AUX1 AUX2 Fig 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration for HVQFN 40 (SOT618-1) PN532_C1 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.6 — 28 November 2017 115436 © NXP B.V. 2017. All rights reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 7.2 Pin description Table 3. PN532 Pin description Symbol Pin Type Ref Description Voltage DVSS 1 PWR LOADMOD 2 O TVSS1 3 PWR TX1 4 O TVDD 5 PWR TX2 6 O TVSS2 7 PWR Digital ground. DVDD Load modulation signal. Transmitter ground. TVDD Transmitter output 1: transmits modulated 13.56 MHz energy carrier. Transmitter power supply. TVDD Transmitter output 2: transmits modulated 13.56 MHz energy carrier.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 3. PN532 Pin description …continued Symbol Pin Type Ref Description Voltage SCK / P72 30 IO PVDD Host interface pin: SPI serial clock. Refer to Table 72 on page 48 for details. Can be used as general purpose IO. PN532_C1 Product data sheet COMPANY PUBLIC P31 / UART_TX 31 IO PVDD General purpose IO/ Debug UART TX. P32_INT0 32 IO PVDD General purpose IO / Interrupt source INT0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8. Functional description 8.1 80C51 The PN532 is controlled via an embedded 80C51 microcontroller core (for more details http://www.standardics.nxp.com/support/documents/microcontrollers/?scope=80C51). Its principle features are listed below: • 6-clock cycle CPU. One machine cycle comprises 6 clock cycles or states (S1 to S6). An instruction needs at least one machine cycle.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.1 PN532 memory map The memory map of PN532 is composed of 2 main memory spaces: data memory and program memory. The following figure illustrates the structure.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.2 Data memory Data memory is itself divided into 2 spaces: • 384-byte IDATA with byte-wide addressing – 258-byte RAM – 128-byte SFR • 1 bank of 64 KB extended RAM (XRAM) with 2-byte-wide addressing 8.1.2.1 IDATA memory The IDATA memory is mapped into 3 blocks, which are referred as Lower IDATA RAM, Upper IDATA RAM, and SFR. Addresses to these blocks are byte-wide, which implies an address space of only 256 bytes.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Address SFR map of NFC controller Bitaddressable IP1 B IE1 ACC I2CC0N PSW T2CON IP0 P3 IE0 S0CON T01CON By
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.2.2 XRAM memory The XRAM memory is divided into 2 memory spaces: • 0000h to 5FFFh: reserved for addressing embedded RAM. For the PN532, only accesses between 0000h and 02FF are valid. • 6000h to 7FFFh: reserved for addressing embedded peripherals. This space is divided into 32 regions of 256 bytes each. Addressing can be performed using R0 or R1 and the XRAMP SFR.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller XRAM FFFFH XRAMP = FFh XRAMP = FFh FFh 00h FFh 00h 40 kB Reserved XRAMP = 82h XRAMP = 81h XRAMP = 80h XRAMP = 7Fh XRAMP = 7Eh MOVX @DPTR,A MOVX A,@DPTR XRAMP = 62h XRAMP = 61h 8000H 7FFFH XRAMP = 60h XRAMP = 5Fh Peripheral 32 XRAMP = 5Eh Peripheral 31 FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h MOVX @Ri,A MOVX A,@Ri PERIPHERAL AREA XRAMP = 42h Peripheral 3 XRAMP = 41h Peripheral 2 6000H 5F
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.4 PCON module The Power Control (PCON) module is configured using the PCON SFR register. Table 7. PCON register (SFR: address 87h) bit allocation Bit 7 Symbol 6 5 4 0 0 0 R/W R R SMOD Reset Access Table 8.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.5.2 Interrupt enable: IE0 and IE1 registers Each interrupt source can be individually enabled or disabled by setting a bit in IE0 or IE1. In register IE0, a global interrupt enable bit can be set to logic 0 to disable all interrupts at once. The 2 following tables describe IE0. Table 10.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller The 2 following tables describe IE1. Table 12. Interrupt controller IE1 register (SFR: address E8h) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 IE1_7 - IE1_5 IE1_4 IE1_3 IE1_2 - IE1_0 Reset Access Table 13. 8.1.5.3 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description of IE1 bits Bit Symbol Description 7 IE1_7 General purpose IRQ interrupt enable.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller The 2 following tables describe IP0. Table 14. Interrupt controller IP0 register (SFR: address B8h) bit allocation Bit Symbol Reset Access Table 15. 7 6 5 4 3 2 1 0 IP0_7 IP0_6 IP0_5 IP0_4 IP0_3 IP0_2 IP0_1 IP0_0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description of IP0 bits Bit Symbol Description 7 IP0_7 Reserved 6 IP0_6 When set to logic 1, NFC-WI interrupt is set to high priority.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.5.4 General purpose IRQ control The general purpose interrupts are controlled by register GPIRQ. NOTE: this is not a standard feature of the 8051. Table 18. GPIRQ register (address 6107h) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 gpirq_ level_ P71 gpirq_ level_ P50 gpirq_ level_ P35 gpirq_ level_ P34 gpirq_ enable _P71 gpirq_ enable_ P50 gpirq_ enable_ P35 gpirq_ enable_ P34 Reset Access Table 19.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.6 Timer0/1 description Timer0/1 are general purpose timer/counters. Timer0/1 has the following functionality: • • • • Configurable edge or level detection interrupts Timer or counter operation 4 timer/counter modes Baud rate generation for Debug UART Timer0/1 comprises two 16-bit timer/counters: Timer0 and Timer1. Both can be configured as either a timer or an event counter.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller The firmware performs a register read in state S5 and a register write in state S6. The hardware loads bits TF0 and TF1 of the register T01CON during state S2 and state S4 respectively. The hardware loads bits IE0 and IE1 of the register T01CON during state S1 and reset these bits during state S2. The registers T0L, T0H, T1L, T1H are updated by the hardware during states S1, S2, S3 and S4 respectively.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.6.2 T01CON register The register is used to control Timer0/1 and report its status. Table 22. Timer0/1 T01CON register (SFR address 88h), bit allocation Bit Symbol Reset Access Table 23.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.6.3 T01MOD register This register is used to configure Timer0/1. Table 24. Timer 0/1 T01MOD register (SFR address 89h), bit allocation Bit Symbol 7 6 5 4 3 2 1 0 GATE1 C/T1 M11 M10 GATE0 C/T0 M01 M00 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Access Table 25. Description of T01MOD bits Bit Symbol Description 7 GATE1 Timer1 gate control. Set by firmware only.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 25. Description of T01MOD bits …continued Bit Symbol Description 3 GATE0 Timer0 gate control. Set by firmware only. When set to logic 1, Timer0 is enabled only when P32_INT0 is high and bit TR0 of register T01CON is set. When set to logic 0, Timer0 is enabled. 2 C/T0 Timer0 timer/counter selector. Set by firmware only. When set to logic 1, Timer0 is set to counter operation.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.6.5 T1L and T1H registers These are the actual timer/counter bytes for Timer1. T1L is the lower byte, T1H is the upper byte. Table 30. Timer0/1 T1L register (SFR address 8Bh), bit allocation Bit Symbol 7 6 5 4 3 2 1 0 T1L.7 T1L.6 T1L.5 T1L.4 T1L.3 T1L.2 T1L.1 T1L.0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Reset Access Table 31. Description of T1L bits Bit Symbol 7 to 0 T1L.7 to T1L.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.6.7 Overflow detection For both the upper and lower bytes of the Timer0/1, an overflow is detected by comparing the incremented value of the most significant bit with its previous value. An overflow occurs when this bit changes from logic 1 to logic 0. An overflow event in the lower byte is clocked into a flip-flop and is used in the next state as the increment enable for the upper byte.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Each increment or decrement of Timer2 occurs in state S1 except when in baud rate generation mode and configured as a counter. In this mode, Timer2 increments on each clock cycle. When configured as a timer, Timer2 is incremented every machine cycle. Since a machine cycle consists of 6 clock periods, the count rate is 1/6 of the CPU clock frequency. 8.1.7.2 T2CON register The register is used to control Timer2 and report its status.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.7.3 T2MOD register This Special Function Register is used to configure Timer2. Table 37. Timer2 T2MOD register (SFR address C9h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - - - - T2RD - DCEN Reset 0 0 0 0 0 0 0 0 Access R R R R R R R/W R/W Table 38. Description of TMOD bits Bit Symbol Description 7 to 3 - Reserved. 2 T2RD Timer2 ReaD flag. Set by hardware and firmware.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.7.4 T2L, T2H registers These are the actual timer/counter bytes. T2L is the lower byte, T2H the upper byte. On the fly reading can give a wrong value since T2H can be changed after T2L is read and before T2H is read. This situation is indicated by flag T2RD in T2MOD. These two 8-bit registers are always combined to operate as one 16-bit timer/counter. Table 39. Bit Symbol Reset Access 7 6 5 4 3 2 1 0 T2L.7 T2L.6 T2L.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.8 Debug UART The Debug UART is implemented to assist debug using UART_RX and UART_TX pins. 8.1.8.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller • Mode 3: – 11 bits are transmitted through UART_TX or received through UART_RX: a start bit (0), 8 data bits (LSB first), a 9th data bit, and a stop bit (1).
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.8.3 S0CON register The Special Function Register S0CON is the control and status register of the Debug UART. This register contains the mode selection bits (SM2, SM1, SM0), the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). Table 48. Debug UART S0CON register (SFR: address 98h) bit allocation Bit Symbol Reset Access Table 49.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 49. Description of S0CON bits …continued Bit Symbol Description 2 RB8 Receive data bit. Set by hardware and by firmware.[1] When set to logic 1: In modes 2 or 3, the hardware stores the 9th data bit that was received in RB8 In mode 1, the hardware stores the stop bit that was received in RB8 In mode 0, the hardware does not change RB8. 1 Transmit interrupt flag [3]. TI must be set to logic 0 by firmware.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.8.4 S0BUF register This register is implemented twice. Writing to S0BUF writes to the transmit buffer. Reading from S0BUF reads from the receive buffer. Only hardware can read from the transmit buffer and write to the receive buffer. Table 51. Debug UART S0BUF Register (SFR: address 99h) bit allocation Bit 7 6 5 Symbol 3 2 1 0 S0BUF[7:0] Reset Access Table 52.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.8.7 Mode 1 and 3 baud rates In modes 1 and 3, the baud rates are determined by the rate of timer1 and timer2 overflow bits: ‘t1_ovf’ and ‘t2_ovf’. The register bit TCLK0 from the register T2CON selects if ‘t1_ovf’ or ‘t2_ovf’ should be used as a source when transmitting. The register bit RCLK0 from the register T2CON selects if ‘t1_ovf’ or ‘t2_ovf’ should be used as a source when receiving.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller When rewriting this formula, the value for the Timer1 reload value T1H is calculated from the desired baud rate as follows: Timer1 reload value T1H (6) SMOD f clk 2 256 – ---------------------------------------------32 6 Baudrate One can achieve very low baud rates with Timer1 by leaving the Timer1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of T01MOD = 0001b), and using the Timer1 interru
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.1.8.9 Baud rates using Timer2 (Debug UART mode 1 and 3) Timer2 has a programming mode to function as baud rate generator for the Debug UART.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller where x is 3 or 7 and n is the bit index. At maximum 4 different controllable modes can be supported. These modes are defined with the following bits: • • • • PxCFGA[n]=0 and PxCFGB[n]=0: Open drain PxCFGA[n]=1 and PxCFGB[n]=0: Quasi Bidirectional (Reset mode) PxCFGA[n]=0 and PxCFGB[n]=1: input (High Impedance) PxCFGA[n]=1 and PxCFGB[n]=1: Push/pull output Px[n] is used to write or read the port value.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.1 Pad configurations description 8.2.1.1 Open-drain DVDD “0” xVDD e_pu e_hd PxCFGA[n] = “0” e_p PxCFGB[n] = “0” 1 Control 2 3 GPIO pad en_n Px[n] zi GND GND CPU_CLK output mode input mode CPU_CLK CPU_CLK Write Px[n] GPIO pad en_n en_n GPIO pad zi Read Px[n] zi Fig 6. Open-drain In open drain configuration, an external pull-up resistor is required to output or read a logic 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.1.2 Quasi Bidirectional DVDD Control xVDD e_pu e_hd PxCFGA[n] = “1” e_p 1 PxCFGB[n] = “0” 2 3 GPIO pad en_n Px[n] zi GND GND CPU_CLK output mode input mode CPU_CLK CPU_CLK Write Px[n] GPIO pad en_n “1” en_n tpushpull e_p “0” e_p e_hd e_hd “1” e_pu e_pu GPIO pad zi zi Read Px[n] Fig 7.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.1.3 Input DVDD “0” xVDD e_pu e_hd PxCFGA[n] = “0” e_p PxCFGB[n] = “1” 1 Control 3 GPIO pad en_n “1” Px[n] 2 zi GND GND CPU_CLK input mode CPU_CLK GPIO pad zi Read Px[n] Fig 8. Input In input configuration, no pull up or hold resistor are internally connected to the pad. PN532_C1 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.1.4 Push-pull output DVDD Control “0” xVDD e_pu e_hd PxCFGA[n] = “1” e_p 1 PxCFGB[n] = “1” 3 GPIO pad en_n Data Px[n] 2 zi GND GND CPU_CLK output mode CPU_CLK Write Px[n] en_n e_p GPIO pad zi Fig 9. Push-pull output In push-pull output, the output pin drives a strong logic 0 or a logic 1 continuously. It is possible to read back the pin output value.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.2 GPIO registers description 8.2.2.1 P7CFGA register Table 60. P7CFGA register (SFR: address F4h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - - - - P7CFGA[2] P7CFGA[1] P7CFGA[0] Reset 1 1 1 1 1 1 1 1 Access R R R R R R/W R/W R/W Table 61. Description of P7CFGA bits Bit Symbol Description 7 to 3 - Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.2.3 P7 register Table 64. P7 register (SFR: address F7h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - - - - P7[2] P7[1] P7[0] Reset 1 1 1 1 1 1 1 1 Access R R R R R R/W R/W R/W Table 65. Bit Description of P7 bits Symbol Description 7 to 3 - Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.2.5 P3CFGB register Table 68. P3CFGB register (SFR: address FDh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - P3CFGB[ 5] P3CFGB[ 4] P3CFGB[ 3] P3CFGB[ 2] P3CFGB[ 1] P3CFGB[ 0] Reset 0 0 0 0 0 0 0 0 Access R R R/W R/W R/W R/W R/W R/W Table 69. Bit Description of P3CFGB bits Symbol 7 to 6 Description Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.2.2.6 P3 register Table 70. Bit P3 register (SFR: address B0h) bit allocation 7 6 5 4 3 2 1 0 Symbol - - P3[5] P3[4] P3[3] P3[2] P3[1] P3[0] Reset 1 1 1 1 1 1 1 1 Access R R R/W R/W R/W R/W R/W R/W Table 71. Description of P3 bits Bit Symbol Description 7 to 6 - Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3 Host interfaces PN532 must be able to support different kind of interfaces to communicate with the HOST. All the interfaces that have to be supported are exclusive. • SPI interface • I2C interface: Standard and Fast modes • High Speed UART (HSU): supporting specific high baud rates PN532 selif(1:0) I2C M I F SPI CPU HSU FIFO Manager HOST RAM Host Interfaces Fig 10. Host interface block diagram 8.3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.1.1 MIF register The Config I0_I1 register is used to select the host interface. It manages also the polarity of P33_INT1. Table 73. Config I0_I1 register (address 6103h) bit allocation Bit 7 Symbol 6 5 int1_pol - 0 0 R/W R Reset Access Table 74.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.2 I2C interface It is recommended to refer the I2C standard for more information. The I2C interface implements a Master/Slave I2C bus interface with integrated shift register, shift timing generation and Slave address recognition. I2C Standard mode (100 kHz SCLK) and Fast mode (400 kHz SCLK) are supported. General Call +W is supported, not hardware General Call (GC +R).
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller In the Slave mode, the I2C interface hardware looks for its own Slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the PN532 microcontroller wishes to become the bus Master, the hardware waits until the bus is free before the Master mode is entered so that a possible Slave action is not interrupted.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller The first byte transmitted contains the Slave address of the transmitting device (7-bit SLA) and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (R). I2C data are received via SDA while P50_SCL outputs the serial clock. I2C data are received 8 bits at a time. After each byte is received, an acknowledge bit is transmitted.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.2.5 Slave transmitter mode The first byte is received and handled as in the Slave receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. I2C data are transmitted via SDA while the serial clock is input through P50_SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.2.7 I2CCON register The CPU can read from and write to this 8-bit SFR. Two bits are affected by the Serial IO (the I2C interface) hardware: the SI bit is set to logic 1 when a serial interrupt is requested, and the STO bit is set to logic 0 when a STOP condition is present on the I2C bus. The STO bit is also set to logic 0 when ENS1 = ‘0’. Table 76.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 77. Description of I2CCON bits …continued Bit Symbol Description 4 STO STOP control. When the STO bit is set to logic 1, while the I2C interface is in Master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the I2C interface hardware automatically sets STO to logic 0. In Slave mode, STO may be set to logic 1 to recover from an error condition.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 77. Bit Description of I2CCON bits …continued Symbol Description 1 to 0 CR[1:0] Serial clock frequency selection in Master mode.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.2.8 I2CSTA register I2CSTA is an 8-bit read-only special function register. The three least significant bits are always at logic 0. The five most significant bits contain the status code. There are 26 possible status codes. When I2CSTA contains F8h, no relevant state information is available and no serial interrupt is requested. Reset initializes I2CSTA to F8h. All other I2CSTA values correspond to defined I2C interface states.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C Master Transmitter Mode status code Status Status of the I2C Bus Code and of the ST[7:0] I2C interface
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C Master Transmitter Mode status code …continued Status Status of the I2C Bus Code and of the ST[7:0] I2C
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C Master Receiver Mode status codes …continued Status Status of the I2C Bus and Code the I2C interface Ha
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C Slave Receiver Mode status codes …continued Status Status of the I2C Bus and Code the I2C interface Har
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C Slave Receiver Mode status codes …continued Status Status of the I2C Bus and Code the I2C interface Har
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx I2C Slave Transmitter Mode status codes …continued Status Status of the I2C Bus and Code the I2C interface
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.2.9 I2CDAT register I2CDAT contains a byte of I2C data to be transmitted or a byte which has just been received. The CPU can read from and write to this 8-bit SFR while it is not in the process of shifting a byte. This occurs when the I2C interface is in a defined state and the serial interrupt flag SI is set to logic 1. Data in I2CDAT remains stable as long as SI is set to logic 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.2.10 I2CADR register The CPU can read from and write to this 8-bit SFR. I2CADR is not affected by the I2C interface hardware. The content of this register is irrelevant when the I2C interface is in a Master mode.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.3 FIFO manager This block is designed to manage a RAM as a FIFO in order to optimize the data exchange between the CPU and the HOST. 8.3.3.1 FIFO manager functional description The RAM used for the FIFO is shared between the SPI and HSU interfaces. Indeed, these interfaces cannot be used simultaneously. The selection of the interface used is done by firmware.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 91. 8.3.3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.3.4 FIFOFS register This register indicates the number of bytes that the CPU can still load into the FIFO until the Transmit FIFO is full. Table 96. Bit FIFOFS register (SFR: address 9Ch) bit allocation 7 6 5 Symbol Access Table 97. 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description of FIFOFS register bits Symbol Description 7 to 0 TransmitFreespace[7:0] 8.3.3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.3.6 SFF register The register bits are used to allow the CPU to monitor the status of the FIFO. The primary purpose is to detect completion of data transfers. Table 100. SFF register (SFR: address 9Eh) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 FIFO_EN - TWLL TFF TFE RWLH RFF RFE 0 0 1 0 1 0 0 1 R/W R R R R R R R Reset Access Table 101.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.3.7 FIT register The FIT register contains 6 read-write bits which are logically OR-ed to generate an interrupt going to the CPU. Table 102. FIT register (SFR: address 9Fh) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 Reset - WCOL_ IRQ TWLL_ IRQ TFF_ IRQ RWLH_ IRQ ROVR_ IRQ RFF_ IRQ Reset 0 0 0 0 0 0 0 0 Access W R R/W R/W R/W R/W R/W R/W Table 103.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.3.8 FITEN register The FITEN register enables or disables the interrupt requests to the CPU. It is also used to reset the content of the Receive and Transmit FIFO. Table 104.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.3.9 FDATA register The FDATA register is used to provide the transmitted and received data bytes. Each data written in the data register is pushed into the Transmit FIFO. Each data read from the data register is popped from the Receive FIFO. Table 106.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.4 HIGH SPEED UART (HSU) The High Speed UART (HSU) provides a high speed link to the host (up to 1.288 Mbit/s). The HSU is a full duplex serial port. The serial port has a Receive-buffer: in conjunction with the FIFO manager, the reception of several bytes can be performed without strong CPU real time constraints.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller tx_data hsu_txout Shift Register tx_shift tr_req TX Control tr_ack tx_clk Prescaler FIFO manager CPU Interface hsu_tx_control hsu_tx_status Baud rate Generator HSU_STA HSU_CTR Baud rate_control HSU_PRE hsu_rcv_status hsu_rcv_control rcv_req_o Preamble rcv_req_i Filter 00 00 FF rcv_ack rx_clk HSU_CNT rx_irq hsu_irq RX Control 1-to-0 Transition Detector rx_start Bit Detector 1FFH rx_shift Input Shift Register rx_data
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.4.1 Mode of operation The HSU supports only one operational mode, which has the following characteristics: • Start bit: – Start bit is detected when a logic 0 is asserted on the HSU_RX line. • 8 data bits: – The data bits are sent or received LSB first. • Stop bit: – During reception, the Stop bit(s) is detected when all the data bits are received and when Stop bit(s) is sampled to logic 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.4.4 HSU wake-up generator The wake-up generator is a 3-bit counter which counts on every rising edge of the HSU_RX pin. When the counter reaches 5, the hsu_on signal is set to logic 1 in order to wake up the PN532. This block is useful in Soft-Power-Down mode. The firmware shall reset this counter just before going in Soft-Power-Down by writing a logic 1 in the hsu_wu_en bit into the HSU_CTR register. 8.3.4.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.4.6 HSU_CTR register This register controls the configuration of the HSU. Table 113. HSU_CTR register (SFR: address ACh) bit allocation Bit Symbol 7 6 hsu_wu_ en start_frame 0 0 0 R/W R/W R/W Reset Access 5 4 3 2 1 0 rx_stopbit tx_en rx_en soft_reset_n 0 0 0 0 1 R/W R/W R/W R/W R/W tx_stopbit[1:0] Table 114. Description of HSU_CTR bits Bit Symbol Description 7 HSU wake-up enable.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.4.7 HSU_PRE register This register is used to configure the baud rate generator prescaler.The prescaler enlarges the range of the counter (at the cost of a lower resolution). The division factor of the prescaler ranges from 1 (20) to 256 (28). Table 115.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.5 Serial Parallel Interface (SPI) The SPI has the following features: • • • • Compliant with Motorola de-facto Serial Peripheral Interface (SPI) standard Synchronous, Serial, Half-Duplex communication, 5 MHz max Slave configuration 8 bits bus interface Through the SPI interface, the host can either access the FIFO manager (acting as data buffer) or the SPI status register.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.5.2 Protocol Once the FIFO is full enough (see FIFO manager thresholds in Table 91 on page 67), the CPU sets bit READY in the SPI Status register to logic 1. Polling the SPI Status register, the host is informed of the READY flag and can start the data transfer. The protocol used is based on: • ADDRESS / DATA protocol for status data exchanges • ADDRESS / DATA / DATA / DATA...
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.5.5 FIFO manager write access MISO is maintained at logic 0. Once a byte is received, a write request is sent to the FIFO manager and the byte is loaded from SPI shift register into Receive FIFO of the FIFO manager. FIFO manager write access DATA MOSI Write N/A MISO DATA DATA DATA DATA 00000000 00000000 00000000 00000000 NSS Fig 17. SPI FIFO manager write access 8.3.5.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Remark: The following figure explains how bits CPOL and CPHA can be used.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.5.7 SPIstatus register The SPIstatus register is byte addressable. It contains bits which are used to monitor the status of the SPI interface, including normal functions, and exception conditions. The primary purpose of this register is to detect completion of a data transfer. The remaining bits in this register are exception condition indicators. Table 124.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.4 Power management Figure 19 “Power management scheme” depicts the internal and external power distribution management. Power is supplied to the PN532 via pins VBAT and PVDD. VBAT is driven by the battery and is used to supply the all blocks excluding the host interface. PVDD is connected to the host’s power supply and powers the PN532’s host interface.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.4.1 Low drop-out voltage regulator 8.4.1.1 LDO block diagram The regulator is used to reduce the VBAT voltage to the typical voltage rating of the PN532. It acts as a 3.0 V linear regulator with resistive feed-back, as long as the VBAT voltage is above 3.4 V. It is designed to cope with a maximum fluctuation of 400 mV on the VBAT line (due to voltage bursts exhibited by the battery). If VBAT falls below 3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.4.1.2 LDO with offset The LDO generates DVDD. When RSTPD_N is high, and PVDD is above 1.6 V, this voltage is defined by: • VBAT > 3.4V: DVDD is fixed at 3V and bursts on VBAT up to 400 mV are suppressed. • 3.4V > VBAT > 2.5V: DVDD follows VBAT with an offset, which decreases with VBAT from 400mV at 3.4V to 0mV at 2.5V. • 2.5V > VBAT > 2.35V: DVDD=VBAT. • 2.35V > VBAT=DVDD and the PN532 is in reset. VBAT 5.5V 3.4V 3.0V DVDD 2.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.4.1.3 LDO without offset The LDO generates DVDD but any voltage fluctuation on VBAT is not compensated for. When RSTPD_N is high and PVDD is above 1.6 V, this voltage is defined by: • VBAT > 3.0V: DVDD = 3 V. • 3.0V > VBAT > 2.35V: DVDD = VBAT. • 2.35V > VBAT=DVDD and the PN532 is in reset. VBAT 5.5V 3.3V 3.0V DVDD 2.35V LDO current consumption few mA <5 uA Fig 23.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.4.1.5 LDO register Table 126. LDO register- (address 6109h) bit allocation Bit 7 6 5 4 Symbol - - Reset 0 0 0 0 Access R R R R/W 3 2 1 0 enoffset soft_ highspeedreg control_ highspeedreg 0 1 0 0 R/W R/W R/W R/W overcurrent_ sel_overcurrent[1:0] status - Table 127. Description of LDO bits Bit Symbol Description 7 to 6 - Reserved 5 Set to logic 1 by PN532 when overcurrent is detected.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.4.2 SVDD switch The SVDD switch is used to control power to the secure IC. The switch is controlled by register Control_switch_rng (address 6106h). The switch is enabled with bit sic_switch_en. When disabled, the SVDD pin is tied to ground. A current limiter is incorporated into the switch. Current consumption exceeding 40 mA triggers the limiter and the status bit sic_switch_overload is set.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5 Power clock and reset controller The PCR controller is responsible for the clock generation, power management and reset mechanism within the PN532. 8.5.1 PCR block diagram The block diagram shows the relationship between the PCR, other embedded blocks and external signals. PN532 CLOCK_CLK 80C51 PCR_int0 CPU_CLK PCR OSC 27.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5.2 27.12 MHz crystal oscillator The 27.12 MHz clock applied to the PN532 is the time reference for the embedded microcontroller. Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to adopt the circuit shown in Figure 24. OSCIN OSCOUT PN532 Crystal 27.12 MHz C C Fig 24. 27.12 MHz crystal oscillator connection 8.5.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5.4 Soft-Power-Down mode (SPD) In order to initiate the Soft-Power-Down mode with minimal power consumption, the firmware should: • Configure I/Os to minimize power consumption. Be careful that for P32_INT0, referring to Section 8.2.1 “Pad configurations description” on page 40, e_hd is forced to logic 1. • Shut down unused functions – Contactless Interface Unit with bit Power-down of SFR register D1h, see Table 179 on page 146.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5.6 Remote wake-up from SPD The PN532 can be woken up from a Soft-Power-Down mode when an event occurs on one of the wake up sources, which has been enabled. There are eight wake-up sources: • • • • • • • • P32_INT0 P33_INT1 RF field detected (RF_DETECT) HSU wake-up (HSU_ON) I2C wake-up (I2C_ON) SPI wake-up (SPI_ON) NFC_WI counters GPIRQ: P34, P35, P50_SCL, P71.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5.8 PCR register description 8.5.8.1 CFR register The Clock Frequency Register is used to select the frequency of the CPU and its associated peripherals. The clock frequency can be changed dynamically by writing to this register at any time. Table 133.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5.8.3 ILR register The Interrupt Level Register is used to program the level of the external interrupts. Firmware can write to this register at any time. Table 137. PCR ILR register (address 6202h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - porpulse_ - enable_pdselif - gpirq_level int1_level int0_level latched Reset 0 1 0 0 0 0 0 0 Access R R/W R R/W R R/W R/W R/W Table 138.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.5.8.4 PCR Control register The Control register is used to perform a firmware reset and clear wake-up conditions in the Status register. Table 139. PCR Control register (address 6203h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - - - - - clear_wakeup_cond soft_reset Reset 1 1 0 0 0 0 0 0 Access R R R R R R R/W R/W Table 140. Description of PCR Control bits Bit Symbol Description 7 to 2 - 8.5.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 142. Description of PCR Status bits Bit Symbol 8.5.8.6 Description 7 i2c_wu I2C wake-up event (on its own address). Set to logic 1, when PN532 woke up due to recognition of its own I2C address appearing on I2C interface[1]. 6 gpirq_wu gpirq wake-up event (or function of P34, P35, P50_SCL and P71 signals when enabled and level-controlled). Set to logic 1, when PN532 woke up from a GIRQ event (GPIRQ at logic 0)[2].
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 144. Description of PCR Wakeupen bits …continued PN532_C1 Product data sheet COMPANY PUBLIC Bit Symbol Description 2 - Reserved. 1 int1_en P33_INT1 wake-up source enable. When set to logic 1, a P33_INT1 event can wake up PN532. 0 int0_en P32_INT0 wake-up source enable. When set to logic 1, a P32_INT0 event can wake up PN532. All information provided in this document is subject to legal disclaimers. Rev. 3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6 Contactless Interface Unit (CIU) The PN532 CIU is a modem for contactless communication at 13.56 MHz. It supports 6 different operating modes • • • • • • ISO/IEC 14443A/MIFARE Reader/Writer. FeliCa Reader/Writer.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.1 Feature list • • • • • • Frequently accessed registers placed in SFR space Highly integrated analog circuitry to demodulate and decode received data Buffered transmitter drivers to minimize external components to connect an antenna.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.2 Simplified block diagram PN532 80C51 Data Mode Detector Serial Data Switch CL UART RF Level Detector Analog Interface Antenna FIFO Contactless Interface Unit Fig 26. Simplify Contactless Interface Unit (CIU) block diagram The Analog Interface handles the modulation and demodulation of the analog signals according to the Card emulation mode, Reader/Writer mode and NFCIP-1 mode communication scheme.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.3 Reader/Writer modes All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimal performance. 8.6.3.1 ISO/IEC 14443A Reader/Writer The following diagram describes the communication on a physical level, the communication overview in the Table 145 describes the physical parameters. 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Fig 28. Data coding and framing according to ISO/IEC 14443A PN532_C1 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.6 — 28 November 2017 115436 © NXP B.V. 2017. All rights reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.3.2 FeliCa Reader/Writer The following diagram describes the communication at the physical level. Table 146 describes the physical parameters. 1. Reader/Writer to Card 8 - 30% ASK, Manchester Coded, Baud rate 212 to 424 kbit/s Battery FeliCa Card PN532 HOST 2. Card to Reader/Writer, >12% ASK load modulation, Manchester Coded, Baud rate 212 to 424 kbit/s Reader/Writer Fig 29.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.3.3 ISO/IEC 14443B Reader/Writer The CIU supports layers 2 and 3 of the ISO/IEC 14443 B Reader/Writer communication scheme, except anticollision which must be implemented in firmware as well as upper layers. The following diagram describes the communication at the physical level. Table 149 describes the physical parameters. 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.4 ISO/IEC 18092, ECMA 340 NFCIP-1 operating mode A NFCIP-1 communication takes place between 2 devices: • Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication. • Target: responds to initiator command either in a load modulation scheme in Passive Communication mode or using a self generated and self modulated RF field for Active Communication mode.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.4.1 ACTIVE Communication mode Active Communication Mode means both the Initiator and the Target are using their own RF field to transmit data. Host PN532 NFC Initiator 1. Initiator starts the communication at selected transfer speed PN532 NFC Target Power to generate the field Host Powered for Digital Communication 2.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.4.2 PASSIVE Communication mode Passive Communication Mode means that the target answers to an Initiator command in a load modulation scheme. Host PN532 NFC Initiator 1. Initiator starts communication at selected transfer speed PN532 NFC Target Power for digital processing Power to generate the field Host 2.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.4.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive communication modes are defined in the NFCIP-1 standard: ISO/IEC 18092 or ECMA 340. 8.6.4.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the ISO/IEC 18092 / ECMA340 NFCIP-1 standard.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.5 Card operating modes The PN532 can be addressed like a FeliCa or ISO/IEC 14443A/MIFARE card. This means that the PN532 can generate an answer in a load modulation scheme according to the ISO/IEC 14443A/MIFARE or FeliCa interface description. Remark: The PN532 does not support a secure storage of data. This has to be handled by a dedicated secure IC or a host. The secure IC is optional.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.5.2 FeliCa Card operating mode With appropriate firmware, the PN532 can handle the FeliCa protocol. The following diagram describes the communication at the physical level. Table 153 describes the physical parameters. 1. Reader/Writer to Card 8 - 30% ASK, Manchester Coded, Baud rate 212 to 424 kbit/s Battery FeliCa Reader/Writer PN532 HOST 2.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller PN532 80C51 CIU State Machine CIU_Command register Control Register bank Programmable timer CIU FIFO control CIU FIFO control CIU interrupt control CIU 64-byte FIFO CRC16 generation & check MIFARE Classic unit Parallel/Serial Converter Random Number Generator Bit Counter Antenna presence Self Test Parity Generation & Check Frame Generation & Check Bit Bit decoding decoding Card Mode Detector Clock generation Filtering Distrib
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.7 Transmitter control The signals delivered by the transmitter are on pins TX1 and pin TX2. The supply and grounds of the transmitter drivers are TVDD, TVSS1 and TVSS2. The signals delivered are the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using a few passive components for matching and filtering, see Section 13 “Application information” on page 212.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PN532_C1 Product data sheet COMPANY PUBLIC Table 154.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TX2 Force TX2CW InVTx2 InvTx2 Envelope TX2 RFEn 100ASK RFON RFOFF GsPMos GsNMos 1 0 1 0 X 0 1 RF 1
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.8 RF level detector The RF level detector is integrated to fulfill NFCIP-1 protocol requirements (e.g. RF collision avoidance). Furthermore the RF level detector can be used to wake up the PN532 and to generate an interrupt. The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register CIU_RFCfg (see Table 245 on page 175).
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.9 Antenna presence self test The goal of the Antenna Presence Self Test is to facilitate at assembly phase the detection of the absence of the antenna and/or antenna matching components. Such a detection is done by mean of measuring the current consumption. Therefore the functionality is guaranteed within a restricted temperature and supply voltage range: • VBAT voltage is above 5 V • Ambient temperature is between 0 and 40 C 8.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Several levels of detection can be programmed through the register to offer a large panel of compatibility to different type of antennas. The high current threshold can be programmed from 40 mA to 150 mA with 15 mA steps (total current consumption of the IC). The low current threshold can be programmed from 5mA to 35 mA with 10 mA step (total current consumption of the IC). There is no dedicated pin for the output of the detector.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.10 Random generator The random generator is used to generate various random number needed for the NFCIP-1 protocol, as well as for MIFARE security. It can also be used for test purpose, by generating random data through the field. Table 159. Data_rng register (address 6105h) bit allocation Bit 7 6 5 4 Symbol 3 2 1 0 data_rng Reset Access X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W Table 160.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 162. Description of Control_switch_rng bits …continued Bit Symbol Description 2 Force the random number generator in running mode. When set to logic 0, the random number generator is under control of the CIU. cpu_need_rng When set to logic 1, the random number generator is forced to run. 1 random_dataready Indicates availability of random number. When set to logic 1, it indicates that a new random number is available.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.12 Serial data switch Two main blocks are implemented in the CIU. A digital block comprising state machines, coder and decoder logic and an analog block with the modulator and antenna drivers, receiver and amplifier. The Serial Data Switch is the interface between these two blocks. The Serial Data Switch can route the interfacing signals to the pins SIGIN and SIGOUT.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller LoadModSel Internal coder invert if INVMOD=1 Tristate TxMIX 0 LOADMOD Envelope 1 AND SIGIN 00 01 10 11 invert if POLSIGN=0 LoadModTst 0 1 RFU TstBusbit 00 01 10 11 Fig 40. Serial data switch for LOADMOD pin PN532_C1 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.6 — 28 November 2017 115436 © NXP B.V. 2017. All rights reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.13 NFC-WI/S2C interface support The NFC-WI/S2C provides the possibility to directly connect a secure IC to the PN532 in order to act as a contactless smart card IC via the PN532. The interfacing signals can be routed to the pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digital ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.13.1 Signal shape for FeliCa NFC-WI/S2C interface support The FeliCa secure IC is connected to the PN532 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal are combined by using the logical function exclusive OR; XOR.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.13.2 Signal shape for ISO/IEC14443A and MIFARE NFC-WI/S2C support The secure IC, e.g. the SmartMX is connected to the PN532 via the pins SIGOUT, SIGIN and P34 / SIC_CLK. The signal at SIGOUT is a digital 13.56 MHz Miller coded signal between PVSS and SVDD. It is either derived from the external 13.56 MHz carrier signal when in Virtual Card Mode or internally generated when in Wired Card mode.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.13.3 NFC-WI/S2C initiator mode The PN532 includes 2 counters of 127 and 31, with digital filtering, to enable activation from the secure IC (ACT_REQ_Si), or the command to go from data to command mode (ESC_REQ). Table 163.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.14.2 Polling sequence functionality for target 1. The 80C51 has to configure the CIU with the correct polling response parameters for the Polling command. 2. To activate the automatic polling in target mode, the AutoColl Command has to be activated. 3. The CIU receives the polling command send out by an initiator and answers with the polling response.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.15 CRC co-processor The CRC preset value of the CRC co-processor can be configured to 0000h, 6363h, A671h or FFFFh depending of the bits CRCPreset in the register Mode.This is only valid when using CalcCRC command (see Section 8.6.20.7 “CalcCRC command” on page 135) During a communication, the preset value of the CRC coprocessor is set according to the bits CIU_RxMode and CIU_TxMode.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.16.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.17 CIU_timer A timer unit is implemented in the CIU: CIU_timer. The 80C51 use CIU_timer to manage timing relevant tasks for contactless communication.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.18 Interrupt request system The CIU indicates certain events by setting interrupt bits in the register CIU_Status1 and, in addition it will set to logic 1 CIU_IRQ_1 or CIU_IRQ_0. If this interrupt is enabled (see Table 12 on page 18) the 80C51 will be interrupted. This allows the implementation of efficient interrupt-driven firmware. 8.6.18.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 165. High priority interrupt sources (CIU_IRQ_0) Interrupt Flag Interrupt source Set automatically, WHEN TxIRq Transmitter a transmitted data stream ends RxIRq Receiver a received data stream ends HiAlertIRq FIFO-buffer the FIFO-buffer is getting full LoAlertIRq FIFO-buffer the FIFO-buffer is getting empty Table 166.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.19.3 Transmitter Power-down The Transmitter Power-down mode switches off the internal antenna drivers to turn off the RF field by setting the bits Tx1RFEn and Tx2RFEn in the register CIU_TxControl to logic 0. The receiver is still switched on, meaning the CIU can be accessed by a second NFC device as a NFCIP-1 target.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.20.3 Commands overview Table 167. Command overview Command Command code Action Idle 0000 No action; cancels current command execution. Config 0001 Configures the CIU for FeliCa, MIFARE and NFCIP-1 communication. Generate RandomID 0010 Generates 10-byte random ID number CalcCRC 0011 Activates the CRC co-processor or perform self-test. Transmit 0100 Transmits data from the FIFO buffer.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller To read out this configuration (after it has been loaded), the command Config with an empty FIFO buffer has to be started. In this case the 25 bytes are transferred from the internal buffer to the FIFO. The CIU has to be configured after each power up, before using the automatic Anticollision/Polling function (AutoColl command). During a Hard-Power-Down (RSTPD_N set to logic 0) this configuration remains unchanged.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.20.10 Receive command The CIU activates the receiver path and waits for any data stream to be received. The correct settings for the expected mode have to be set before starting this command. This command terminates automatically when the reception ends and the active command is Idle.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Each transmission process has to be started with setting bit StartSend in the register CIU_BitFraming. This command has to be cleared by firmware by writing any command to the CIU_Command register e.g. the command idle. Note: If the bit RxMultiple in register CIU_RxMode is set, this command will never leave the receiving state, because the receiving will not be cancelled automatically. 8.6.20.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Fig 46. AutoColl command • NFCIP-1 106 kbps passive communication mode: The MIFARE anticollision is finished and the command changes automatically to Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.20.13 MFAuthent command This command handles the MIFARE authentication in Reader/Writer mode to enable a secure communication to any MIFARE Clasic 1K and MIFARE Classic 4K emulation card.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.21 CIU tests signals 8.6.21.1 CIU self-test The CIU has the capability to perform a self-test. To start the self-test the following procedure has to be performed: 1. Perform a SoftReset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config command. 3. Enable the self-test by writing the value 09h to the register CIU_AutoTest. 4. Write 00h to the FIFO. 5. Start the self-test with the CalcCRC command. 6.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.21.2 CIU test bus The test bus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the PN532. The test bus allows to route internal signals to output pins. The Observe_testbus register is used to enable this functionality. Table 169.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.21.3 Test signals at pin AUX Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register CIU_AnalogTest. See Table 279 on page 185 8.6.21.4 PRBS Enables the Pseudo Random Bit Stream of 9-bit or 15-bit length sequence, PRBS9 or PRBS15, according to ITU-TO150. To start the transmission of the defined datastream, Transmit command has to be activated.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.22 CIU memory map The registers of the CIU are either map into the SFR or into the XRAM memory space. Table 173.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 174.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23 CIU register description 8.6.23.1 CIU register bit behavior Depending of the functionality of a register, the access condition to the bits can vary. The following table describes the access conditions: Table 175. Behavior of register bits Abbreviation Behavior R/W Read and Write Description These bits can be written and read by the 80C51.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.3 CIU_Command register (D1h or 6331h) Starts and stops the command execution. Table 178. CIU_Command register (address D1h or 6331h) bit allocation Bit 7 6 5 4 Symbol - - RcvOff Power-down 3 2 1 0 Command Reset 0 0 1 0 0 0 0 0 Access R R R/W DY DY DY DY DY Table 179.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.4 CIU_CommIEn register (D2h or 6332h) Control bits to enable and disable the passing of interrupt requests. Table 180. CIU_CommIEn register (address D2h or 6332h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - TxIEn RXIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Reset 0 0 0 0 0 0 0 0 Access R R/W R/W R/W R/W R/W R/W R/W Table 181. Description of CIU_CommIEn bits Bit 8.6.23.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.6 CIU_CommIrq register (D4h or 6334h) Contains common CIU interrupt request flags. Table 184. CIU_CommIrq register (address D4h or 6334h) bit allocation Bit Symbol 7 6 5 4 Set1 TxIRq RxIRq IdleIrq 3 2 HiAltertIRq LoAlertIRq 1 0 ErrIRq TimerIRq Reset 0 0 0 1 0 1 0 0 Access W DY DY DY DY DY DY DY Table 185.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.7 CIU_DivIrq register (D5h or 6335h) Contains miscellaneous interrupt request flags. These bits are latched. Table 186. CIU_DivIrq register (address D5h or 6335h) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 Set2 - - SiginActIrq ModeIRq CRCIRq RfOnIRq RfOffIRq Reset 0 0 0 X 0 0 X X Access W R R DY DY DY DY DY Table 187.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.8 CIU_Error register (D6h or 6336h) Error flags showing the error status of the last command executed. Table 188. CIU_Error register (address D6h or 6336h) bit allocation Bit Symbol 7 6 5 4 3 2 1 0 WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocollErr Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 189.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.9 CIU_Status1 register (DFh or 6337h) Contains status flags of the CRC, Interrupt Request System and FIFO buffer. Table 190. CIU_Status1 register (address DFh or 6337h) bit allocation Bit 7 6 5 4 3 2 1 0 CIU_IRQ_ 1 CRCOk CRCReady CIU_IRQ _0 TRunning RFOn HiAlert LoAlert Reset 0 0 1 0 0 X 0 1 Access R R R R R R R R Symbol Table 191.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.10 CIU_Status2 register (E9h or 6338h) Contain status flags of the receiver, transmitter and Data Mode Detector. Table 192. CIU_Status2 register (address E9h or 6338h) bit allocation Bit Symbol 7 6 5 4 3 TempSensClear - RFFreqOK TgActivated MFCrypto1On Reset Access 2 1 0 ModemState[2:0] 0 0 0 0 0 0 0 0 R/W R R DY DY R R R Table 193.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.11 CIU_FIFOData register (EAh or 6339h) In- and output of 64 byte FIFO buffer. Table 194. CIU_FIFOData register (address EAh or 6339h) bit allocation Bit 7 6 5 4 Symbol Reset Access 3 2 1 0 FIFOData[7:0] X X X X X X X X DY DY DY DY DY DY DY DY Table 195. Description of CIU_FIFOData bits 8.6.23.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.13 CIU_WaterLevel register (ECh or 633Bh) Defines the thresholds for FIFO under- and overflow warning. Table 198. CIU_WaterLevel register (address ECh or 633Bh) bit allocation Bit 7 6 Symbol - - 5 4 3 2 1 0 WaterLevel[6:0] Reset 0 0 0 0 1 0 0 0 Access R R R/W R/W R/W R/W R/W R/W Table 199. Description of CIU_WaterLevel bits Bit Symbol Description 7 to 6 - Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.15 CIU_BitFraming register (EEh or 633Dh) Adjustments for bit oriented frames. Table 202. CIU_BitFraming register (address EEh or 633Dh) bit allocation Bit 7 Symbol 6 StartSend 5 4 3 RxAlign[2:0] 2 - 1 0 TxLastBits[2:0] Reset 0 0 0 0 0 0 0 0 Access W R/W R/W R/W R R/W R/W R/W Table 203.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.16 CIU_Coll register (EFh or 633Eh) Defines the first bit collision detected on the RF interface. Table 204. CIU_Coll register (address EFh or 633Eh) bit allocation Bit Symbol 7 6 5 ValuesAfterColl - CollPosNotValid Reset Access 4 3 2 1 0 CollPos 1 0 1 X X X X X R/W R R R R R R R Table 205.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.17 CIU_Mode register (6301h) Defines general modes for transmitting and receiving. Table 206. CIU_Mode register (address 6301h) bit allocation Bit 7 Symbol Reset Access 6 MSBFirst DetectSync 5 TXWaitRF 4 3 2 1 RxWaitRF PolSigin ModeDet Off 0 CRCPreset [1:0] 0 0 1 1 1 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Table 207.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.18 CIU_TxMode register (6302h) Defines the transmission data rate and framing during transmission. Table 208. CIU_TxMode register (address 6302h) bit allocation Bit 7 Symbol 6 TxCRCEn Reset Access 5 4 TxSpeed[2:0] 3 2 InvMod TxMix 1 0 TxFraming[1:0] 0 0 0 0 0 0 0 0 R/W DY DY DY R/W R/W DY DY Table 209.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.19 CIU_RxMode register (6303h) Defines the reception data rate and framing during receiving. Table 210. CIU_RxMode register (address 6303h) bit allocation Bit 7 Symbol 6 RXCRCEn Reset Access 5 4 RxSpeed[2:0] 3 2 RxNoErr RxMultiple 1 0 RxFraming[1:0] 0 0 0 0 0 0 0 0 R/W DY DY DY R/W R/W DY DY Table 211.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.20 CIU_TxControl register (6304h) Controls the logical behavior of the antenna driver pins TX1 and TX2. See alsoTable 154 on page 114 and Table 155 on page 114. Table 212.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.21 CIU_TxAuto register (6305h) Controls the setting of the antenna driver. Table 214. CIU_TxAuto register (address 6305h) bit allocation Bit 7 Symbol 5 Auto Force AutoWakeUp RFOFF 100ASK Reset Access 6 4 - 3 2 CAOn InitialRFOn 1 0 Tx2 RFAutoEn Tx1 RFAutoEn 0 0 0 0 0 0 0 0 R/W R/W R/W R R/W W R/W R/W Table 215.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.22 CIU_TxSel register (6306h) Selects the sources for the analogue transmitter part Table 216. CIU_TxSel register (address 6306h) bit allocation Bit 7 Symbol Reset Access 6 5 LoadModSel[1:0] 4 3 DriverSel[1:0] 2 1 0 SigOutSel[3:0] 0 0 0 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 217.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 217. Description of CIU_TxSel bits …continued Bit Symbol Description 1000-1011 FeliCa secure IC modulation 1000 RX* 1001 TX 1010 Demodulator comparator output 1011 Reserved Note: * To have a valid signal the CIU has to be set to the receiving mode by either the Transceive or Receive commands.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.24 CIU_RxThreshold register (6308h) Selects thresholds for the bit decoder. Table 220. CIU_RxThreshold register (address 6308h) bit allocation Bit 7 6 Symbol 5 4 3 MinLevel[3:0] Reset Access 2 - 1 0 Collevel[2:0] 1 0 0 0 0 1 0 0 R/W R/W R/W R/W R R/W R/W R/W Table 221. Description of CIU_RxThreshold bits 8.6.23.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.26 CIU_FelNFC1 register (630Ah) Defines the length of the FeliCa Sync bytes and the minimum length of the received frame. Table 224. CIU_FelNFC1 register (address 630Ah) bit allocation Bit Symbol Reset Access 7 6 5 4 FelSyncLen[1:0] 3 2 1 0 DataLenMin[5:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 225.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.27 CIU_FelNFC2 register (630Bh) Defines the maximum length of the received frame. Table 226. CIU_FelNFC2 register (address 630Bh) bit allocation Bit Symbol 7 6 WaitForSelected ShortTimeSlot 0 R/W Reset Access 5 4 3 0 0 0 0 R/W R/W R/W R/W 2 1 0 0 0 0 R/W R/W R/W DataLenMax[5:0] Table 227.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.28 CIU_MifNFC register (630Ch) Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or card operating mode. Table 228. CIU_MifNFC register (address 630Ch) bit allocation Bit 7 Symbol Reset Access 6 5 4 SensMiller[2:0] 3 TauMiller[1:0] 2 1 MFHalted 0 TxWait[1:0] 0 1 1 0 0 0 1 0 R/W R/W R/W R/W R/W DY R/W R/W Table 229.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.29 CIU_ManualRCV register (630Dh) Allows manual fine tuning of the internal receiver. IMPORTANT NOTE: For standard application it is not recommended to change this register settings. Table 230.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 231. Description of CIU_ManualRCV bits …continued Bit Symbol Description 3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL for clock recovery is extended. Note: As the bandwidth is extended, the PLL filtering effect is weaker and the performance of the communication may be affected.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.30 CIU_TypeB register (630Eh) Selects the specific settings for the ISO/IEC 14443B Table 232. CIU_TypeB register (address 630Eh) bit allocation Bit 7 Symbol Reset Access 6 Rx Rx SOFReq EOFReq 5 4 3 2 - EOFSOF Width NoTx SOF NoTx EOF 1 0 TxEGT[1:0] 0 0 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W Table 233.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.31 CIU_CRCResultMSB register (6311h) Shows the actual MSB values of the CRC calculation. Note: The CRC is split into two 8-bit registers. See also the CIU_CRCResultLSB register. Note: Setting the bit MSBFirst in CIU_Mode register reverses the bit order, the byte order is not changed Table 234.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.33 CIU_GsNOff register (6313h) Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when there is no RF generated by the PN532. Table 238. CIU_GsNOff register (address 6313h) bit allocation Bit 7 Symbol Reset Access 6 5 4 3 CWGsNOff[3:0] 2 1 0 ModGsNOff[3:0] 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 239.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.34 CIU_ModWidth register (6314h) Controls the setting of the modulation width. Table 240. CIU_ModWidth register (address 6314h) bit allocation Bit 7 6 5 Symbol Reset Access 4 3 2 1 0 ModWidth[7:0] 0 0 1 0 0 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 241.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.35 CIU_TxBitPhase register (6315h) Adjust the bit phase at 106 kbit/s during transmission. Table 242. CIU_TxBitPhase register (address 6315h) bit allocation Bit Symbol 7 6 5 4 RcvClkChange Reset Access 3 2 1 0 TxBitPhase[6:0] 1 0 0 0 0 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Table 243.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.36 CIU_RFCfg register (6316h) Configures the receiver gain and RF level detector sensitivity. Table 244. CIU_RFCfg register (address 6316h) bit allocation Bit Symbol 7 RFLevelAmp Reset Access 6 5 4 3 RxGain[2:0] 2 1 0 RFLevel[3:0] 0 1 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 245.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.37 CIU_GsNOn register (6317h) Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when generating RF. Table 246. CIU_GsNOn register (address 6317h) bit allocation Bit 7 6 Symbol Reset Access 5 4 3 CWGsNOn[3:0] 2 1 0 ModGsNOn[3:0] 1 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 247.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.38 CIU_CWGsP register (6318h) Defines the conductance of the P-driver. Table 248. CIU_CWGsP register (address 6318h) bit allocation Bit 7 6 Symbol - - 5 4 3 2 1 0 CWGsP[5:0] Reset 0 0 1 0 0 0 0 0 Access R R R/W R/W R/W R/W R/W R/W Table 249. Description of CIU_CWGsP bits Bit Symbol Description 7 to 6 - Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.40 CIU_TMode register (631Ah) Defines settings for the internal timer. Table 252. CIU_TMode register (address 631Ah) bit allocation Bit 7 Symbol TAuto Reset Access 6 5 TGated[1:0] 4 3 TAutoRestart 2 1 0 TPrescaler_Hi[3:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 253.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.41 CIU_TPrescaler register (631Bh) Define the LSB of the Timer-Prescaler. Table 254. CIU_TPrescaler register (address 631Bh) bit allocation Bit 7 6 5 Symbol Reset Access 4 3 2 1 0 TPrescaler_LO[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 255. Description of CIU_TPrescaler bits Bit Symbol Description 7 to 0 TPrescaler_LO[7:0] Defines lower 8 bits for TPrescaler.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.43 CIU_TReloadVal_lo register (631Dh) Defines the LSB of the 16 bit long timer reload value. Table 258. CIU_TReload_lo register (address 631Dh) bit allocation Bit 7 6 5 Symbol 3 2 1 0 TReloadVal_Lo[7:0] Reset Access 4 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 259.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.46 CIU_TestSel1 register (6321h) General test signal configuration. Table 264. CIU_TestSel1 register (address 6321h) bit allocation Bit 7 Symbol LoadModTst[1:0] Reset Access 6 5 4 SICclksel[1:0] 3 2 SICClkD1 1 0 TstBusBitSel[2:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 265.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.47 CIU_TestSel2 register (6322h) General test signal configuration and PRBS control. Table 266. CIU_TestSel2 register (address 6322h) bit allocation Bit Symbol 7 6 5 TstBusFlip PRBS9 PRBS15 0 0 R/W R/W Reset Access 4 3 2 0 0 0 R/W R/W R/W 1 0 0 0 0 R/W R/W R/W TstBusSel[4:0] Table 267.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.49 CIU_TestPinValue register (6324h) Defines the values for the 7 bit test bus signals to be I/O on P70_IRQ, RSTOUT_N, P35, P34 / SIC_CLK, P33_INT1, P32_INT0, P31 / UART_TX and P30 / UART_RX pins. Table 270. CIU_TestPinValue register (address 6324h) bit allocation Bit Symbol 7 5 4 useio Reset Access 6 3 2 1 0 TestPinValue[6:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 271.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.51 CIU_AutoTest register (6326h) Controls the digital self-test. Table 274. CIU_AutoTest register (address 6326h) bit allocation Bit 7 6 5 4 Symbol - AmpRcv - - 3 2 1 0 SelfTest[3:0] Reset 0 1 0 0 0 0 0 0 Access R R R R R/W R/W R/W R/W Table 275. Description of CIU_AutoTest bits Bit Symbol Description 7 - Reserved.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.53 CIU_AnalogTest register (6328h) Controls the pins AUX1 and AUX2. Table 278. CIU_AnalogTest register (address 6328h) bit allocation Bit 7 Symbol Reset Access 6 5 4 3 AnalogSelAux1[3:0] 2 1 0 AnalogSelAux2[3:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 279. Description of CIU_AnalogTest bits Bit Symbol Description 7 to 4 AnalogSelAux1[3:0] Controls the AUX1 pin.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 279. Description of CIU_AnalogTest bits …continued Bit Symbol 3 to 0 AnalogSelAux2[3:0] Controls the AUX2 pin. Note: All test signals are described in Section 8.6.21.3 “Test signals at pin AUX” on page 142.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.54 CIU_TestDAC1 register (6329h) Defines the test value for TestDAC1. Table 280. CIU_TestDAC1 register (address 6329h) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - Reset 0 0 X X TestDAC1[5:0] X X X X Access R R R/W R/W R/W R/W R/W R/W Table 281. Description of CIU_TestDAC1 bits Bit Symbol Description 7 to 6 - Reserved. 5 to 0 TestDAC1[5:0] Defines the test value for TestDAC1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.23.57 CIU_RFlevelDet register (632Fh) Power down of the RF level detector. Table 286. CIU_RFlevelDet register (address 632Fh) bit allocation Bit 7 6 5 4 3 2 1 0 Symbol - - - pd_rflvldet - - - - Reset Access 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Table 287. Description of CIU_RFlevelDet bits Bit Symbol Description 7 to 5 - Reserved. These bits must be set to logic 0.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PN532_C1 Product data sheet COMPANY PUBLIC 8.7.1 Standard registers Table 288.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register address Bit7 Bit6 630Bh CIU_FelNFC2 WaitForSelected 630Ch CIU_MifNFC 630Dh CIU_ManualRCV
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register address Register name Bit7 Bit6 Bit5 Bit4 Bit3 6330h SIC_CLK sic_clk_p34_en 6331h CIU_Co
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SFR address Register name 99h S0BUF 9Ah RWL 9Bh TWL 9Ch FIFOFS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SFR address Register name Bit7 Bit6 Bit5 D4h CIU_CommIrq Set1 D5h CIU_DivIrq Set2 D6h CIU_Error
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 9. Limiting values Table 290. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit PVDD Supply Voltage -0.5 4 V VBAT Power Supply Voltage -0.5 6.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12. Characteristics Unless otherwise specified, the limits are given for the full operating conditions. The typical value is given for 25C, VBAT = 3.4 V and PVDD = 3 V. Timings are only given from characterization results. 12.1 Power management characteristics Table 293. Power management characteristics Symbol Parameter Conditions Min Typ VBAT Battery power supply range VSS = 0 V 2.7 5.5 V VDVDD LDO output VBAT > 3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.3 Current consumption characteristics Table 295. Current consumption characteristics Symbol PN532_C1 Product data sheet COMPANY PUBLIC Parameter Conditions Min Typ Max Unit 2 A 25 45 A 18 40 A 3 10 mA [2] 0.5 45 mA Switch closed [3] 3 30 mA Transmitter supply current Continuous wave, VBAT = 3.4 V [1] 60 100 mA Total supply current Continuous wave, VBAT = 3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.4 Antenna presence self test thresholds The following values are guaranteed by design. Testing is done in production for cases andet_ithl[1:0]=10b and for andet_ithh[2:0]=011b. The operating range is: • VBAT voltage above 5V • Ambient temperature between 0 and 40°C Table 296.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.6 Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT) Table 299. Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT) Symbol Parameter Conditions CinOSCIN OSCIN Input Capacitance AVDD = 2.8 V, VDC = 0.65 V, VAC = 0.9 Vpp Min Typ Max Unit 2 pF VOHOSCOUT High level output voltage 1.1 V VOLOSCOUT Low level output voltage 0.2 V 2 pF 27.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.8 Input pin characteristics for I0 and I1 Table 301. Input pin characteristics for I0, I1 and TESTEN Symbol Parameter Conditions Min Typ Max Unit High level input voltage [1] 0.7 DVDD DVDD V VIL Low level input voltage [2] 0 0.3 DVDD V IIH High level input current I0 and I1 VI = DVDD -1 1 A IIL Low level input current VI = 0 V -1 1 A Cin Input capacitance VIH 2.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.10 Input/output characteristics for pin P70_IRQ Table 303. Input/output pin characteristics for pin P70_IRQ Symbol Parameter Conditions Unit 0.7 PVDD PVDD VIL Low level input voltage [2] 0 0.3 PVDD V VOH Push-pull mode high level output voltage 0.7 PVDD PVDD V 0.7 PVDD PVDD V 0 0.3 PVDD V 0 0.3 PVDD V PVDD = 3 V, IOH = -4 mA PVDD = 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.11 Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1 Table 304. Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1 Symbol Parameter Conditions Unit 0.7 PVDD PVDD VIL Low level input voltage [2] 0 0.3 PVDD V VOH Push-pull mode high level output voltage PVDD - 0.4 PVDD V PVDD - 0.4 PVDD V 0 0.4 V 0 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.12 Input/output pin characteristics for P34 / SIC_CLK Table 305. Input/output pin characteristics for P34 / SIC_CLK Symbol Parameter Conditions Min Typ Max Unit High level input voltage [1] 0.7 SVDD SVDD VIL Low level input voltage [2] 0 0.3 SVDD V VOH Push-pull mode high level VBAT = 3.4 V, output voltage IOH = -4 mA SVDD - 0.4 SVDD V VOL Push_pull mode low level VBAT = 3.4 V, output voltage IOL = 4 mA 0 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.14 Input pin characteristics for NSS / P50_SCL / HSU_RX Table 307. Input pin characteristics for NSS / HSU_RX for HSU / SPI interfaces Symbol Parameter Conditions High level Input voltage VIH PVDD > 1.6V Min [1] Typ Max 0.7 PVDD PVDD Unit V [3] VIL Low level Input voltage PVDD > 1.6V 0 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.15 Input/output pin characteristics for MOSI / SDA / HSU_TX Table 309. Input/output pin characteristics for MOSI / HSU_TX for HSU and SPI Interfaces Symbol Parameter Conditions High level Input voltage VIH Min [1] Typ Max 0.7 PVD Unit PVDD V 0.3 PVD V D [2] Low level Input voltage VIL 0 D VOH HSU_TX high level output voltage PVDD = 3 V, IOH = -4 mA PVDD =1.8 V, IOH = -2 mA [3] PVDD - 0.4 PVDD V PVDD - 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.16 Input/output pin characteristics for MISO / P71 and SCK / P72 Table 311. Input/output pin characteristics for MISO / P71 and SCK / P72 Symbol Parameter Conditions Min Typ Max Unit High level Input voltage [1] 0.7 PVDD PVDD VIL Low level Input voltage [2] 0 0.3 PVDD V VOH Push_pull / MISO mode high level output voltage PVDD - 0.4 PVDD V PVDD - 0.4 PVDD V 0 0.4 V 0 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.18 Output pin characteristics for SIGOUT Table 313. Output pin characteristics for SIGOUT Symbol Parameter Conditions Min Typ Max Unit VOH High level output voltage DVDD - 0.1 < SVDD < DVDD IOH = -4 mA SVDD - 0.4 SVDD V VOL Low level output voltage DVDD - 0.1 < SVDD < DVDD IOL = +4 mA 0 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.20 Input pin characteristics for RX Table 315. Input pin characteristics for RX Symbol Parameter Conditions Min VINRX Dynamic Input voltage Range VBAT = 3.4 V -1 Product data sheet COMPANY PUBLIC Unit AVDD +1 V Cinrx RX Input Capacitance 10 pF Rinrx RX Input Series resistance VBAT = 3.4 V, Receiver active, VRX = 1 Vpp, 1.5 V DC offset 350 VRX,MinIV,Mill Minimum Dynamic Input voltage, Miller coded VBAT = 3.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Fig 47. RX Voltage definitions 12.21 Output pin characteristics for AUX1/AUX2 Table 316. Output pin characteristics for AUX1/AUX2 Symbol Parameter Conditions Min Typ Max Unit VOH High level output voltage VBAT = 3.4 V, IOH = -4 mA DVDD - 0.4 DVDD V VOL Low level output voltage VBAT = 3.4 V, IOL = 4 mA DVSS DVSS +0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.23 Timing for Reset and Hard-Power-Down VBAT DVDD 2.4 V 60 mV RSTPD_N Tresetpon Thpd Tresetrstpd RSTOUT_N Fig 48. Timings for reset overview Table 318. Reset duration time Symbol Tresetpon Reset time at power on THPD Hard Power-Down time TresetRSTPD_N Reset time when RSTPD_N is released [1] PN532_C1 Product data sheet COMPANY PUBLIC Parameter Conditions [1] User dependent Min Typ Max 0.1 0.4 2 20 [1] 0.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.24 Timing for the SPI compatible interface Table 319. SPI timing specification Symbol Parameter Conditions Min Typ Max tSCKL SCK low pulse width 50 ns tSCKH SCK high pulse width 50 ns tSHDX SCK high to data changes 25 ns tDXSH data changes to SCK high 25 ns tSLDX SCK low to data changes tSLNH SCK low to NSS high 25 0 Unit ns ns Fig 49.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.25 Timing for the I2C interface Table 320. I2C timing specification Symbol Parameter Conditions Min Typ Max Unit fSCL SCL clock frequency 400 kHz tHD; STA Hold time (repeated) START condition.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 13. Application information Battery SVDD PMU Secure SIGOUT VBAT Core SIGIN DVDD 4.7uF P34 / SIC_CLK X7R or X5R PN532 100nF CRx 1nF 100nF RX AVDD R1 1 k 100nF R2 2.7 k VMID Cvmid 100nF TVDD 4.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 14. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-1 terminal 1 index area A E A1 c detail X C e1 e 1/2 e 20 y y1 C v M C A B w M C b 11 L 21 10 e e2 Eh 1/2 1 e 30 terminal 1 index area 40 31 Dh X 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) 5 mm max.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 15. Abbreviations Table 321. Abbreviations PN532_C1 Product data sheet COMPANY PUBLIC Acronym Description ASK Amplitude Shift keying BPSK Bit Phase Shift Keying CIU Contactless Interface Unit CRC Cyclic Redundancy Check ECMA European Computer Manufacturers Association organization GPIO General Purpose Input Output GPIRQ General Purpose Interrupt ReQuest HPD Hard Power Down (see Section 8.5.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 16. Revision history Table 322. Revision history Document ID Release date Data sheet status Change notice Supersedes PN532_C1 v. 3.6 20171128 Product data sheet - PN532_C1 v. 3.5 Modifications: PN532_C1 v. 3.5 Modifications: PN532_115434 Modifications: PN532_115433 Modifications: • Security status changed into Company Public, no content change 20120920 • • - PN532_115434 Section 17.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Table 322. Revision history …continued Document ID Release date Data sheet status 115421 2 June 2006 Preliminary data sheet Revision 2.0 115420 11 May 2006 Preliminary data sheet Revision 1.2 115412 21 December 2005 Objective data sheet 115411 24 October 2005 Objective data sheet 115410 17 October 2005 Objective data sheet PN532_C1 Product data sheet COMPANY PUBLIC Change notice Supersedes Revision 1.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.2 8.1.2.1 8.1.2.2 8.1.3 8.1.4 8.1.5 8.1.5.1 8.1.5.2 8.1.5.3 8.1.5.4 8.1.6 8.1.6.1 8.1.6.2 8.1.6.3 8.1.6.4 8.1.6.5 8.1.6.6 8.1.6.7 8.1.7 8.1.7.1 8.1.7.2 8.1.7.3 8.1.7.4 8.1.7.5 8.1.8 8.1.8.1 8.1.8.2 8.1.8.3 8.1.8.4 8.1.8.5 8.1.8.6 8.1.8.7 8.1.8.8 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . .
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.3.4.5 8.3.4.6 8.3.4.7 8.3.4.8 8.3.5 8.3.5.1 8.3.5.2 8.3.5.3 8.3.5.4 8.3.5.5 8.3.5.6 8.3.5.7 8.4 8.4.1 8.4.1.1 8.4.1.2 8.4.1.3 8.4.1.4 8.4.1.5 8.4.2 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.8.1 8.5.8.2 8.5.8.3 8.5.8.4 8.5.8.5 8.5.8.6 8.6 8.6.1 8.6.2 8.6.3 8.6.3.1 8.6.3.2 8.6.3.3 8.6.4 8.6.4.1 8.6.4.2 8.6.4.3 8.6.4.4 8.6.5 8.6.5.1 HSU_STA register . . . . . . . . . . . . . . . . . . . . . 76 HSU_CTR register . . . . . .
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 8.6.21.1 8.6.21.2 8.6.21.3 8.6.21.4 8.6.22 8.6.23 8.6.23.1 8.6.23.2 8.6.23.3 8.6.23.4 8.6.23.5 8.6.23.6 8.6.23.7 8.6.23.8 8.6.23.9 8.6.23.10 8.6.23.11 8.6.23.12 8.6.23.13 8.6.23.14 8.6.23.15 8.6.23.16 8.6.23.17 8.6.23.18 8.6.23.19 8.6.23.20 8.6.23.21 8.6.23.22 8.6.23.23 8.6.23.24 8.6.23.25 8.6.23.26 8.6.23.27 8.6.23.28 8.6.23.29 8.6.23.30 8.6.23.31 8.6.23.32 8.6.23.33 8.6.23.34 8.6.23.35 8.6.23.36 8.6.23.37 8.6.23.38 8.6.23.39 8.6.23.
PN532/C1 NXP Semiconductors Near Field Communication (NFC) controller 12.25 13 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20 21 Timing for the I2C interface . . . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . .
