Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 124 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.13.1 Signal shape for FeliCa NFC-WI/S
2
C interface support
The FeliCa secure IC is connected to the PN532 via the pins SIGOUT and SIGIN.
The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized
demodulated signal. The clock and the demodulated signal are combined by using the
logical function exclusive OR; XOR.
To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
The time delay for the digital filtering is in the range of one bit length. The demodulated
signal changes only at a positive edge of the clock.
The register CIU_TxSel (see Table 217 on page 162
) controls the setting at SIGOUT
Remark: The PN532 differs from the ECMA 373 specification, by the fact that when in
FeliCa card emulation mode, the PN532 does send preamble bytes at 212kbps on
SIGOUT as soon as the PN532 detects RF field.
Remark: In FeliCa card emulation mode, when the PN532 mode detector is activated, the
data sent on SIGOUT are clocked at the received data rate only after the SYNC bytes are
received. If per default the FeliCa card emulation mode is expected at 212kpbs, the
424kbps may need specific implementation at application level: the PN532 will sent
beginning of first received frame (preamble+SYNC bytes) at 212kbps.
Remark: To properly work in FeliCa wired card mode, the SIGIN signal generated by the
FeliCa secure element must be synchronous with the received SIGOUT bit clock, and the
bit RCVOFF in the register 6331h (or SFR register D1h) must be set to logic level 1. The
phase relationship of the SIGIN and SIGOUT bit clocks must respect a modulo[4]
13.56MHz clock cycles.
The response from the FeliCa secure IC is transferred from SIGIN directly to the antenna
driver. The modulation is done according to the register setting of the antenna drivers.
The 13.56MHz clock can be switched to P34 / SIC_CLK (see sic_clk_p34_en bit in
Table 177 on page 145
).
Remark: The signal on antenna is shown in principle only. This signal is sinusoidal. The
clock for SIGIN is the same as the clock for SIGOUT.
Fig 42. Signal shape for SIGOUT in FeliCa secure IC mode
Fig 43. Signal shape for SIGIN in FeliCa secure IC mode
clock
demodulated
signal
signal on
SIGOUT
clock
signal on
SIGIN
signal on
antenna