Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 128 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.15 CRC co-processor
The CRC preset value of the CRC co-processor can be configured to 0000h, 6363h,
A671h or FFFFh depending of the bits CRCPreset in the register Mode.This is only valid
when using CalcCRC command (see Section 8.6.20.7 “
CalcCRC command” on page
135)
During a communication, the preset value of the CRC coprocessor is set according to the
bits CIU_RxMode and CIU_TxMode.
The CRC polynomial for the 16-bit CRC is fixed to x
16
+ x
12
+ x
5
+ 1.
The CRC co-processor is configurable to handle the different MSB and LSB requirements
for the different protocols.The bit MSBFirst in the register CIU_Mode indicates that the
data will be loaded with MSB first
The registers CRCResult-Hi and CRCResult-Lo indicate the result of the CRC calculation.
8.6.16 FIFO buffer
An 64*8 bits FIFO buffer is implemented in the CIU. It buffers the input and output data
stream between the 80C51 and the internal state machine of the CIU. Thus, it is possible
to handle data streams with lengths of up to 64 bytes without taking timing constraints into
account.
8.6.16.1 Accessing the FIFO buffer
The FIFO-buffer input and output data bus is connected to the register CIU_FIFOData.
Writing to this register stores one byte in the FIFO-buffer and increments the internal
FIFO-buffer write-pointer. Reading from this register shows the FIFO-buffer contents
stored at the FIFO-buffer read-pointer and decrements the FIFO-buffer read-pointer. The
distance between the write- and read-pointer can be obtained by reading the register
CIU_FIFOLevel.
When the 80C51 starts a command, the CIU may, while the command is in progress,
access the FIFO-buffer according to that command. Physically only one FIFO-buffer is
implemented, which can be used in input- and output direction. Therefore the 80C51 has
to take care, not to access the FIFO-buffer in an unintended way.
8.6.16.2 Controlling the FIFO buffer
Besides writing to and reading from the FIFO-buffer, the FIFO-buffer pointers might be
reset by setting the bit FlushBuffer in the register CIU_FIFOLevel. Consequently, the
FIFOLevel[6:0] bits are set to logic 0, the bit BufferOvfl in the register CIU_Error is set to
logic 0, the actually stored bytes are not accessible anymore and the FIFO-buffer can be
filled with another 64 bytes again.