Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 145 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.23 CIU register description
8.6.23.1 CIU register bit behavior
Depending of the functionality of a register, the access condition to the bits can vary. The
following table describes the access conditions:
8.6.23.2 CIU_SIC_CLK_en register (6330h)
Enables the use of P34 / SIC_CLK as secure IC clock.
Table 175. Behavior of register bits
Abbreviation Behavior Description
R/W Read and
Write
These bits can be written and read by the 80C51. Since they are used
only for control means, there content is not influenced by internal
state machines, e.g. CIU_CommIEn may be written and read by the
CPU. It will also be read by internal state machines, but never
changed by them.
DY DYnamic These bits can be written and read by the 80C51. Nevertheless, they
may also be written automatically by CIU internal state machines, e.g.
the commands in the CIU_Command register change their values
automatically after their execution.
R Read only These registers hold flags, which value is determined by CIU internal
states only, e.g. the CRCReady register can not be written from
external but shows CIU internal states.
W Write only These registers are used for control means only. They may be written
by the 80C51 but can not be read. Reading these registers returns
always logic 0.
Reserved These registers are not implemented or reserved for NXP testing use.
Table 176. CIU_SIC_CLK_en register (address 6330h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol sic_clk_p34_en - - - Errorbusbitenable Errorbusbitsel[2:0]
Reset 0 000 0 000
Access R/W R R R R/W R/W R/W R/W
Table 177. Description of CIU_SIC_CLK_en bits
Bit Symbol Description
7 sic_clk_p34_en Set to logic 1, this bit configures P34 / SIC_CLK to be used as secure
IC clock: SIC_CLK.
Set to logic 0, P34 / SIC_CLK is in normal mode: P34.
6 to 4 - Reserved
3 Errorbusbitenable Set to logic 1, enable the error source selected by Errorbusbitsel on
AUX pads according to SelAux1 and SelAux2 bits (code 1010b).
2 to 0 Errorbusbitsel[2:0] Define the error source on ErrorBusBit:
Value Description
000 selects ProtocollErr on test bus
001 selects ParityErr on test bus
010 selects CRCErr on test bus
011 selects CollErr on test bus
100 selects BufferOvfl on test bus
101 selects RFErr on test bus
110 selects TempErr on test bus
111 selects WrErr on test bus