Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 16 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.4 PCON module
The Power Control (PCON) module is configured using the PCON SFR register.
8.1.5 Interrupt Controller
The interrupt controller has the following features:
• 13 interrupt sources
• Interrupt enable registers IE0 and IE1
• Interrupt priority registers IP0 and IP1
• Wake-up from Power-Down state
8.1.5.1 Interrupt vectors
The mapping between interrupt sources and interrupt vectors is shown in Table 9
.
Table 7. PCON register (SFR: address 87h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SMOD - CPU_PD -
Reset 000000 0 0
Access R/WRRRRRR/WR/W
Table 8. Description of PCON bits
Bit Symbol Description
7SMODSerial MODe:
When set to logic 1, the baud rate of the Debug UART is doubled
6 to 3 - Reserved.
1CPU_PDPower-down:
When set to logic 1, the microcontroller goes in Power-down mode
0 Reserved This bit should only ever contain logic 0.
Table 9. Interrupt vector
Interrupt
number
Interrupt
vector
Interrupt sources Incremental priority level
(conflict resolution level)
0 0003h External P32_INT0 Highest
1 000Bh Timer0 interrupt
2 0013h External P33_INT1
3 001Bh Timer1 interrupt
4 0023h Debug UART interrupt
5 002Bh Timer2 interrupt
6 0033h NFC-WI interrupt
7 003Bh LDO overcurrent interrupt
8 0043h Reserved
9 004Bh CIU interrupt 1
10 0053h CIU interrupt 0
11 005Bh I
2
C interrupt
12 0063h SPI, FIFO, or HSU interrupts
13 006Bh Reserved
14 0073h General Purpose IRQ Lowest