Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 30 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.7.4 T2L, T2H registers
These are the actual timer/counter bytes. T2L is the lower byte, T2H the upper byte.
On the fly reading can give a wrong value since T2H can be changed after T2L is read
and before T2H is read. This situation is indicated by flag T2RD in T2MOD.
These two 8-bit registers are always combined to operate as one 16-bit timer/counter.
8.1.7.5 RCAP2L, RCAP2H registers
These are the reload bytes. In the reload mode the T2H/T2L counters are loaded with the
values found in the RCAP2H/RCAP2L registers respectively.
Table 39. Timer2 T2L register (SFR address CCh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol T2L.7 T2L.6 T2L.5 T2L.4 T2L.3 T2L.2 T2L.1 T2L.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 40. Description of T2L bits
Bit Symbol Description
7 to 0 T2L.7 to T2L.0 Timer2 timer/counter lower byte
Table 41. Timer2 T2H register (SFR address CDh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol T2H.7 T2H.6 T2H.5 T2H.4 T2H.3 T2H.2 T2H.1 T2H.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 42. Description of T2H bits
Bit Symbol Description
7 to 0 T2H.7 to T2H.0 Timer2 timer/counter upper byte
Table 43. Timer2 RCAP2L register (SFR address CAh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol R2L.7 R2L.6 R2L.5 R2L.4 R2L.3 R2L.2 R2L.1 R2L.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 44. Description of RCAP2L bits
Bit Symbol Description
7 to 0 R2L.7 to R2L.0 Timer2 lower reload byte
Table 45. Timer2 RCAP2H register (SFR address CBh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol R2H.7 R2H.6 R2H.5 R2H.4 R2H.3 R2H.2 R2H.1 R2H.0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 46. Description of RCAP2H bits
Bit Symbol Description
7 to 0 R2H.7 to R2H.0 Timer2 upper reload byte