Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 51 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
In the Slave mode, the I
2
C interface hardware looks for its own Slave address and the
general call address. If one of these addresses is detected, an interrupt is requested.
When the PN532 microcontroller wishes to become the bus Master, the hardware waits
until the bus is free before the Master mode is entered so that a possible Slave action is
not interrupted. If bus arbitration is lost in the Master mode, the I
2
C interface switches to
the Slave mode immediately and can detect its own Slave address in the same serial
transfer.
8.3.2.2 Master transmitter mode
As a Master, the I
2
C logic will generate all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial
transfer, the I
2
C bus will not be released.
I
2
C data are output through SDA while P50_SCL outputs the serial clock. The first byte
transmitted contains the Slave address of the receiving device (7-bit SLA) and the data
direction bit. In this case the data direction bit (R/W) will be a logic ‘0’ (W). I
2
C data are
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
In the Master transmitter mode, a number of data bytes can be transmitted to the Slave
receiver. Before the Master transmitter mode can be entered, I
2
CCON must be initialized
with the ENS1 bit set to logic 1 and the STA, STO and SI bits set to logic 0. ENS1 must be
set to logic 1 to enable the I
2
C interface. If the AA bit is set to logic 0, the I
2
C interface will
not acknowledge its own Slave address or the general call address if they are present on
the bus. This will prevent the I
2
C interface from entering a Slave mode.
The Master transmitter mode may now be entered by setting the STA bit. The I
2
C
interface logic will then test the I
2
C bus and generate a start condition as soon as the bus
becomes free. When a START condition is transmitted, the serial interrupt flag (SI) is set
to logic 1, and the status code in the status register (I
2
CSTA) will be 08h. This status code
must be used to vector to an interrupt service routine that loads I
2
CDAT with the Slave
address and the data direction bit (SLA+W). The SI bit in I
2
CCON must then be set to
logic 0 before the serial transfer can continue.
When the Slave address and the direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set to logic 1 again,
and a number of status codes in I
2
CSTA are possible. The appropriate action to be taken
for any of the status codes is detailed in Table 80 on page 58
. After a repeated start
condition (state 10h), the I
2
C interface may switch to the Master receiver mode by loading
I
2
CDAT with SLA+R.
8.3.2.3 Master receiver mode
As a Master, the I
2
C logic will generate all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial
transfer, the I
2
C bus will not be released.