Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 53 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.2.5 Slave transmitter mode
The first byte is received and handled as in the Slave receiver mode. However, in this
mode, the direction bit will indicate that the transfer direction is reversed. I
2
C data are
transmitted via SDA while the serial clock is input through P50_SCL. START and STOP
conditions are recognized as the beginning and end of a serial transfer.
In the Slave transmitter mode, a number of data bytes are transmitted to a Master
receiver. Data transfer is initialized as in the Slave receiver mode. When I
2
CADR and
I
2
CCON have been initialized, the I
2
C interface waits until it is addressed by its own Slave
address followed by the data direction bit which must be ‘1’ (R) for the I
2
C interface to
operate in the Slave transmitter mode. After its own Slave address and the R bit have
been received, the serial interrupt flag (SI) is set to logic 1 and a valid status code can be
read from I
2
CSTA. This status code is used to vector to an interrupt service routine, and
the appropriate action to be taken for each of these status codes is detailed in Table 83 on
page 62. The Slave transmitter mode may also be entered if arbitration is lost while the
I
2
C interface is in the Master mode.
If the AA bit is set to logic 0 during a transfer, the I
2
C interface will transmit the last byte of
the transfer and enter state C0h or C8h. the I
2
C interface is switched to the not addressed
Slave mode and will ignore the Master receiver if it continues the transfer. Thus the
Master receiver receives all ‘1’s as I
2
C data. While AA is set to logic 0, the I
2
C interface
does not respond to its own Slave address or a general call address. However, the I
2
C
bus is still monitored, and address recognition may be resumed at any time by setting AA.
This means that the AA bit may be used to temporarily isolate the I
2
C interface from the
I
2
C bus.
8.3.2.6 I
2
C wake-up mode
The wake up block can only be used when I
2
C is configured as a Slave.
It is a dedicated circuitry, separated from the main I
2
C peripheral which functionality is to
wake-up the PN532 from Soft-Power-Down mode.
Before entering the Soft-Power-Down mode, the following actions must be taken:
• Enable the block and select the wake-up conditions (see Table 90 on page 65).
• Enable the I
2
C wake-up event in the PCR (see Table 143 on page 97)
Once in Soft-Power-Down mode, the wake up block will monitor the I
2
C bus. If it
recognizes its own address and the command type is valid (read only, write only, or both
depending of settings in register i
2
c_wu_control, see Table 90 on page 65), the wake up
block will generate an acknowledge, stretch P50_SCL, configure the I
2
C interface in Slave
Transmitter or Slave Receiver mode depending on the command. Finally, i
2
c_on is set to
logic 1, which initiates the wake-up sequence (see Section 8.5 “
Power clock and reset
controller” on page 90).
When the microcontroller has been woken up, the firmware must identify the wake up
source and must disable the wake up block (see Table 90 on page 65
) to use I
2
C. It is now
the I
2
C peripheral which stretches P50_SCL.
To enable wake up on GC +W, the LSB bit of I
2
CADR should be set to logic 1 (see
Table 88 on page 65
). The wake-up block and the wake-up on a write command should be
enabled before entering in Soft-Power-Down mode. When the wake up on GC +W
condition is recognized, the behavior is the same as described above.