Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 72 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.3.3.9 FDATA register
The FDATA register is used to provide the transmitted and received data bytes. Each data
written in the data register is pushed into the Transmit FIFO. Each data read from the data
register is popped from the Receive FIFO.
8.3.3.10 FSIZE register
This register defines the size of the Receive FIFO. The maximum size is 182 bytes. The
free space not used by the Receive FIFO in the RAM will be allocated to Transmit FIFO.
Table 106. FDATA register (SFR: address A2h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FDATA[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 107. Description of FDATA bits
Bit Symbol Description
7 to 0 FDATA[7:0] Writing to FDATA writes to the transmit buffer.
Reading from FDATA reads from the receive buffer.
Table 108. FSIZE register (SFR: address A3h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ReceiveSize[7:0]
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 109. Description of FSIZE bits
Bit Symbol Description
7 to 0 ReceiveSize[7:0] Size of the Receive FIFO