Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 92 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.5.4 Soft-Power-Down mode (SPD)
In order to initiate the Soft-Power-Down mode with minimal power consumption, the
firmware should:
• Configure I/Os to minimize power consumption. Be careful that for P32_INT0,
referring to Section 8.2.1 “
Pad configurations description” on page 40, e_hd is forced
to logic 1.
• Shut down unused functions
– Contactless Interface Unit with bit Power-down of SFR register D1h, see Table 179
on page 146.
– Disable the SVDD switch, see Table 129 on page 89
– Power down the RF level detector if RF wake up is not enabled, see Table 287 on
page 188.
• Enable relevant wake-up sources
• Disable unwanted interrupts
• Assert bit CPU_PD in register PCON, see Table 7 on page 16
When bit CPU_PD is set, all clocks are stopped and the LDO is put into Soft-Power-Down
mode. Finally, the Power Sequencer goes into Stopped state.
8.5.5 Low power modes
There are 2 different low power modes.
• Hard-Power-Down mode (HPD): controlled by the pin RSTPD_N. The PN532 goes
into reset and power consumption is at a minimum, see Section 8.5.3 “
Reset modes”.
• Soft-Power-Down mode (SPD): controlled by firmware. See Section 8.5.4
“Soft-Power-Down mode (SPD)” to optimize the power consumption in this mode.
Table 131. Current consumption in low power modes
Mode Conditions Maximum current consumption
Hard-Power-Down RSTPD_N is set to logic 0 2 A
Soft-Power-Down
with no RF detector
Sequence of Section 8.5.4
is applied 40 A
Soft-Power-Down
with RF detector active
Sequence of Section 8.5.4
is applied 45 A