WT1231H W T 12 3 1H IS M T RANS CEIV ER M O D U L E V 1 .3 TAL GENERAL DESCRIPTION ND The WT1231H is a transceiver module capable of operation over a wide frequency range, including the 315,433,868 and 915MHz license-free ISM (Industry Scientific and Medical) frequency bands. All major RF communication parameters are programmable and most of them can be dynamically set. The WT1231H offers the unique advantage of programmable narrow-band and wide- band communication modes.
WT1231H Table of Contents 1. Page General Description ................................................................................................................................................ 8 1.1. Simplified Block Diagram ............................................................................................................................. 8 1.2. Pin and Marking Diagram...........................................................................................................................
WT1231H 3.4.8. Complex Filter - OOK ............................................................................................................................... 27 3.4.9. RSSI ......................................................................................................................................................... 27 3.4.10. 3.4.11. 3.4.12. 3.4.13. 3.4.14. 3.4.15. 3.4.16. 3.4.17. Cordic ........................................................................................................
WT1231H 5.4.3. Rx Processing .......................................................................................................................................... 50 5.5. Packet Mode .................................................................................................................................................. 50 5.5.1. General Description................................................................................................................................... 50 5.5.2.
WT1231H Index of Figures Page Figure 1. Block Diagram ................................................................................................................................................ 8 Figure 2. Pin Diagram .................................................................................................................................................... 9 Figure 3. Marking Diagram ..............................................................................................................
WT1231H Figure 41. +20dBm Schematic .................................................................................................................................... 77 Figure 42. Package Outline Drawing ........................................................................................................................... 78 Index of Tables Page Table 1. WT1231H Pinouts .................................................................................................................................
WT1231H Acronyms BOM BR BW CCITT CRC DAC ETSI FCC Fdev FIFO FIR FS FSK GUI IC ID IF IRQ ITU LFSR LNA LO Bill Of Materials Bit Rate Bandwidth Comité Consultatif International Téléphonique et Télégraphique - ITU Cyclic Redundancy Check Digital to Analog Converter European Telecommunications Standards Institute Federal Communications Commission Frequency Deviation First In First Out Finite Impulse Response Frequency Synthesizer Frequency Shift Keying Graphical User Interface Integrated Circuit IDentificator I
WT1231H This product datasheet contains a detailed description of the WT1231H performance and functionality. 1. General Description The WT1231H is a transceiver module ideally suited for today's high performance ISM band RF applications. It is intended for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bidirectional RF links, and where stable and constant RF performance is required over the full operating range of the device down to 1.8V.
WT1231H 1.2. Pin and Marking Diagram The following diagram shows the pin arrangement of the top view. Figure 3.
WT1231H 1.3. Pin Description Table 1 WT1231H Pinouts Number Name Type Description S 1 RESET I/O 2 DIO0 I/O Digital I/O, software configured 3 DIO1 I/O Digital I/O, software configured 4 DIO2 I/O Digital I/O, software configured 5 DIO3 I/O Digital I/O, software configured 6 DIO4 I/O Digital I/O, software configured 7 DIO5 I/O Digital I/O, software configured 8 3.3V - Supply voltage 9 GND - Reset trigger input Ground RF signal output/input.
WT1231H 2. Electrical Characteristics 2.1. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Symbol Description Min Max Unit VDDmr Supply Voltage -0.5 3.
WT1231H 2.3 Module Specification The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1= VBAT2=VDD=3.3 V, temperature = 25 °C, FRF = 915 MHz, Pout = +20dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. Note Unless otherwise specified, the performances in the other frequency bands are similar or better. 2.3.1.
WT1231H FSTEP Frequency synthesizer step FSTEP = FXOSC/219 - 61.0 - Hz FRC RC Oscillator frequency After calibration - 62.5 - kHz BRF Bit rate, FSK Programmable 1.2 - 300 kbps BRO Bit rate, OOK Programmable 1.2 - 32.768 kbps FDA Frequency deviation, FSK Programmable FDA + BRF/2 =< 500 kHz 0.6 - 300 kHz 2.3.3. Receiver All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a PN15 sequence with a BER of 0.
WT1231H * -23 +20 -18 - dBm dBm Programmable 2.6 - 500 kHz Image rejection in OOK mode Wanted signal level = -106 dBm 27 30 - dB TS_RE Receiver wake-up time, from PLL locked state to RxReady RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s - 1.7 96 - ms us TS_RE_AGC Receiver wake-up time, from PLL locked state, AGC enabled RxBw = 10 kHz, BR = 4.8 kb/s RxBw = 200 kHz, BR = 100 kb/s - 3.
WT1231H 2.3.5. Digital Specification Conditions: Temp = 25°C, VDD = 3.3V, unless otherwise specified. Table 8 Digital Specification Symbol Description VIH Conditions Min Typ Max Unit Digital input level high 0.8 - - VDD VIL Digital input level low - - 0.2 VDD VOH Digital output level high Imax = 1 mA 0.9 - - VDD VOL Digital output level low Imax = -1 mA - - 0.
WT1231H 3. Module Description This section describes in depth the architecture of the WT1231H low-power, highly integrated transceiver. 3.1. Power Supply Strategy The WT1231H employs an advanced power supply scheme, which provides stable operating characteristics over the full temperature and voltage range of operation. This includes the full output power of +20dBm maintained from 2.4 to 3.6V. The WT1231H can be powered from any low-noise voltage source via pins VBAT1 and VBAT2.
WT1231H 3.2.2. CLKOUT Output The reference frequency, or a fraction of it, can be provided on DIO5 by modifying bits ClkOut in RegDioMapping2. Two typical applications of the CLKOUT output include: To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset. To provide an oscillator reference output.
WT1231H 3.2.4. Lock Time PLL lock time TS_FS is a function of a number of technical factors, such as synthesized frequency, frequency step, etc. When using the built-in sequencer, the WT1231H optimizes the startup time and automatically starts the receiver or the transmitter when the PLL has locked.
WT1231H 3.3. Transmitter Description The transmitter of WT1231H comprises the frequency synthesizer, modulator and power amplifier blocks. 3.3.1. Architecture Description LNA Receiver Chain RFIO PA0 Local Oscillator PA1 PA_BOOST PA2 Figure 5. Transmitter Block Diagram 3.3.2.
WT1231H Table 9 Bit Rate Examples Type Classical modem baud rates (multiples of 1.2 kbps) Classical modem baud rates (multiples of 0.9 kbps) Round bit rates (multiples of 12.5, 25 and 50 kbps) Watch Xtal frequency BitRate (15:8) BitRate (7:0) (G)FSK (G)MSK OOK Actual BR (b/s) 0x68 0x2B 1.2 kbps 1.2 kbps 1200.015 0x34 0x15 2.4 kbps 2.4 kbps 2400.060 0x1A 0x0B 4.8 kbps 4.8 kbps 4799.760 0x0D 0x05 9.6 kbps 9.6 kbps 9600.960 0x06 0x83 19.2 kbps 19.2 kbps 19196.
WT1231H 3.3.5. Modulation Shaping Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp. In FSK mode, a Gaussian filter with BT = 0.3, 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta modulator.
WT1231H 3.3.7.
WT1231H 3.4. Receiver Description The WT1231H features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is, however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected.
WT1231H 3.4.3. Automatic Gain Control By default (LnaGainSelect = 000), the LNA gain is controlled by a digital AGC loop in order to obtain the optimal sensitivity/ linearity trade-off. Regardless of the data transfer mode (Packet or Continuous), the following series of events takes place when the receiver is enabled: The receiver stays in WAIT mode, until RssiValue exceeds RssiThreshold for two consecutive samples. Its power consumption is the receiver power consumption.
WT1231H Table 13 Receiver Performance Summary Input Power Pin Gain Setting Pin < AgcThresh1 AgcThresh1 < Pin < AgcThresh2 AgcThresh2 < Pin < AgcThresh3 AgcThresh3 < Pin < AgcThresh4 AgcThresh4 < Pin < AgcThresh5 AgcThresh5 < Pin G1 G2 G3 G4 G5 G6 P-1dB [dBm] -37 -31 -26 -14 >-6 >0 Receiver Performance (typ) NF IIP3 IIP2 [dB] [dBm] [dBm] 7 13 18 27 36 44 -18 -15 -8 -1 +13 +20 +35 +40 +48 +62 +68 +75 3.4.3.1.
WT1231H 3.4.5. Quadrature Mixer - ADCs - Decimators The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high IIP2 and IIP3 responses.
WT1231H 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 10b / 24 01b / 20 00b / 16 4 4 3 3 3 2 2 2 1 1 1 0 0 0 25.0 31.3 41.7 50.0 62.5 83.3 100.0 125.0 166.7 200.0 250.0 333.3 400.0 500.0 12.5 15.6 20.8 25.0 31.3 41.7 50.0 62.5 83.3 100.0 125.0 166.7 200.0 250.0 3.4.7. DC Cancellation DC cancellation is required in zero-IF architecture transceivers to remove any DC offset generated through selfreception.
WT1231H Note - RssiValue can only be read when it exceeds RssiThreshold - The receiver is capable of automatic gain calibration, in order to improve the precision of its RSSI measurements. This function injects a known RF signal at the LNA input, and calibrates the receiver gain accordingly.
WT1231H 3.4.11. FSK Demodulator The FSK demodulator of the WT1231H is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10: 0.5 δ ® The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.4.13), to provide the companion processor with a synchronous data stream in Continuous mode. 3.4.12.
WT1231H 3.4.12.1. Optimizing the Floor Threshold OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Note that the noise floor of the receiver at the demodulator input depends on: The noise figure of the receiver. The gain of the receive chain from antenna to base band.
WT1231H 3.4.13. Bit Synchronizer The Bit Synchronizer is a block that provides a clean and synchronized digital output, free of glitches. Its output is made available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum receiver performance its use when running Continuous mode is strongly advised. The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in RegBitrate.
WT1231H signed result is loaded in FeiValue in RegFei, in 2’s complement format. The time required for an FEI evaluation is 4 times the bit period.
WT1231H When the AFC is automatically triggered (AfcAutoOn = 1), the user has the option to: Clear the former AFC correction value, if AfcAutoClearOn = 1 Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the LO keeps on drifting in the “same direction”. Ageing compensation is a good example. The WT1231H offers an alternate receiver bandwidth setting during the AFC phase, to accommodate large LO drifts.
WT1231H 3.4.17. Temperature Sensor When temperature is measured, the receiver ADC is used to digitize the sensor response. Most receiver blocks are disabled, and temperature measurement can only be triggered in Standby or Frequency Synthesizer modes. The response of the temperature sensor is -1°C / Lsb. A CMOS temperature sensor is not accurate by nature, therefore it should be calibrated at ambient temperature for precise temperature readings.
WT1231H 4. Operating Modes 4.1. Basic Modes The circuit can be set in 5 different basic modes which are described in Table 16. By default, when switching from a mode to another one, the sub-blocks are woken up according to a pre-defined and optimized sequence. Alternatively, these operating modes can be selected directly by disabling the automatic sequencer (SequencerOff in RegOpMode = 1).
WT1231H 4.2.1. Transmitter Startup Time The transmitter wake-up time, TS_TR, is given by the sequence controlled by the digital part. It is a pure digital delay which depends on the bit rate and the ramp-up time. In FSK mode, this time can be derived from the following equation. , where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time.
WT1231H Rx startup request (sequencer or user) XO Started and PLL is locked TS_RE Analog FE’s group delay Channel Filter’s group delay DC Cutoff’s group delay RSSI sampling RSSI sampling Tana Tcf Tdcc Trssi Trssi Reception of Packet ModeReady RxReady Received Packet Preamble may start Figure 18.
WT1231H 4.2.4. Rx Start Procedure As described in the former sections, the RxReady interrupt warns the uC that the receiver is ready. In Continuous mode with Bit Synchronizer, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur. In Continuous mode without Bit Synchronizer, valid data will be available on DIO2/DATA right after the RxReady interrupt.
WT1231H 4.3. Listen Mode The circuit can be set to Listen mode, by setting ListenOn in RegOpMode to 1 while in Standby mode. In this mode, WT1231H spends most of the time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is woken up and listens for an RF signal. If a wanted signal is detected, the receiver is kept on and the data is demodulated.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET Notes - the accuracy of the typical timings given in Table 17 will depend in the RC oscillator calibration - RC oscillator calibration is required, and must be performed at power up. See section 4.3.5 for details 4.3.2. Criteria The criteria taken for detecting a wanted signal and hence deciding to maintain the receiver on is defined by ListenCriteria in RegListen1.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET Upon detection of a valid packet, the sequencing is altered, as shown below: PayloadReady ListenCriteria passed Idle Rx Idle Rx Idle Rx ListenEnd = 00 Listen Mode Mode ListenEnd = 01 Listen Mode Idle Rx ListenEnd = 10 Listen Mode Figure 22. Listen Mode Sequence (wanted signal is received) 4.3.4.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 4.4. AutoModes Automatic modes of packet handler can be enabled by configuring the related parameters in RegAutoModes. The intermediate mode of the module is called IntermediateMode and the enter and exit conditions to/from this intermediate mode can be configured through the parameters EnterCondition & ExitCondition. The enter and exit conditions cannot be used independently of each other i.e. both should be enabled at the same time.
WT1231H 5. Data Processing 5.1. Overview 5.1.1. Block Diagram Figure below illustrates the WT1231H data processing circuit. Its role is to interface the data to/from the modulator/ demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. The circuit contains several control blocks which are described in the following paragraphs. DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 Tx/Rx CONTROL Data Rx SYNC RECOG.
WT1231H 5.2. Control Block Description 5.2.1. SPI Interface The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. Three access modes to the registers are provided: SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access.
WT1231H The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is actually a special case of FIFO / BURST mode with only 1 data byte transferred. During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. 5.2.2. FIFO 5.2.2.1.
WT1231H FifoLevel 1 0 B B+1 # of bytes in FIFO Figure 27. FifoLevel IRQ Source Behavior Note - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be dynamically updated by only changing the FifoThreshold parameter - FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation 5.2.2.4.
WT1231H Rx DATA Bit N-x = (NRZ) Sync_value[x] Bit N-1 = Bit N = Sync_value[1] Sync_value[0] DCLK SyncAddressMatch Figure 28. Sync Word Recognition During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.3.1.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.4. Continuous Mode 5.4.1. General Description As illustrated in Figure 29, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive. DIO0 DIO1/DCLK DIO2/DATA DIO3 DIO4 DIO5 Tx/Rx CONTROL Data Rx SYNC RECOG. SPI NSS SCK MOSI MISO Figure 29. Continuous Mode Conceptual View 5.4.2.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.4.3. Rx Processing If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided. Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated below. DATA (NRZ) DCLK Figure 31.
WT1231H DVANCED COMMUNICATIONS & SENSING DATASHEET DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 CONTROL Data Rx SYNC RECOG. PACKET HANDLER FIFO (+SR) SPI NSS SCK MOSI MISO Tx Figure 32. Packet Mode Conceptual View Note The Bit Synchronizer is automatically enabled in Packet mode. 5.5.2. Packet Format 5.5.2.1. Fixed Length Packet Format Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater than 0.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET DC free Data encoding CRC checksum calculation AES Enc/Dec Preamble 0 to 65535 bytes Sync Word 0 to 8 bytes Address byte Message Up to 255 bytes CRC 2-bytes Payload (min 1 byte) Fields added by the packet handler in Tx and processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 33. Fixed Length Packet Format 5.5.2.2.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.5.2.3. Unlimited Length Packet Format Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can then transmit and receive packet of arbitrary length and PayloadLength register is not used in Tx/Rx modes for counting the length of the bytes transmitted/received. This mode is a replacement for the legacy buffered mode in RF63/RF64 transceivers.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET The transmission of packet data is initiated by the Packet Handler only if the module is in Tx mode and the transmission condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is met to transmit the packet data.
WT1231H As shown in Figure 33 and Figure 34 above the message part of the Packet can be encrypted and decrypted with the cipher 128- cipher key stored in the configuration registers. 5.5.5.1. Tx Processing 1. User enters the data to be transmitted in FIFO in Stdby/Sleep mode and gives the transmit command. 2.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.5.6. Handling Large Packets When Payload length exceeds FIFO size (66 bytes) whether in fixed, variable or unlimited length packet format, in addition to PacketSent in Tx and PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below: For Tx: FIFO can be prefilled in Sleep/Standby but must be refilled "on-the-fly" during Tx with the rest of the payload.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.5.7.2. Address Based Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). Two address based filtering options are available: AddressFiltering = 01: Received address field is compared with internal register NodeAddress.
WT1231H ADVANCED COMMUNICATIONS & SENSING data input X15 DATASHEET CRC Polynomial =X16 + X12 + X5 + 1 X14 X13 X12 X11 X5 *** X4 X0 *** Figure 36. CRC Implementation 5.5.8. DC-Free Data Mechanisms The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 5.5.8.2. Data Whitening Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved. The whitening/de-whitening process is enabled if DcFree = 10.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 6. Configuration and Status Registers 6.1.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET Address Register Name Reset (built-in) Default (recom mended) 0x1A RegAfcBw 0x8A 0x8B 0x1B RegOokPeak 0x40 OOK demodulator selection and control in peak mode 0x1C RegOokAvg 0x80 Average threshold control of the OOK demodulator 0x1D RegOokFix 0x06 Fixed threshold control of the OOK demodulator 0x1E RegAfcFei 0x10 AFC and FEI control and status 0x1F RegAfcMsb 0x00 MSB of the frequency correction of the AFC 0x20 RegAfcLsb 0x00
WT1231H Default (recom mended) Reset (built-in) Address Register Name 0x3E-0x4D RegAesKey1-16 0x00 16 bytes of the cypher key 0x4E RegTemp1 0x01 Temperature Sensor control 0x4F RegTemp2 0x00 Temperature readout 0x58 RegTestLna 0x1B Sensitivity boost 0x5A RegTestPa1 0x55 High Power PA settings 0x5C RegTestPa2 0x70 High Power PA settings 0x6F RegTestDagc 0x71 RegTestAfc 0x00 0x50 + RegTest - Note 0x00 0x30 Description Fading Margin Improvement AFC offset for low modula
WT1231H 6.2.
WT1231H ADVANCED COMMUNICATIONS & SENSING RegBitrateLsb (0x04) 7-0 BitRate(7:0) rw RegFdevMsb (0x05) 7-6 5-0 7-0 Fdev(13:8) Fdev(7:0) r rw rw RegFdevLsb (0x06) DATASHEET 0x0b LSB of Bit Rate (Chip Rate if Manchester encoding is enabled) FXO SC BitRate = ---------------------------------BitRate(15,0) Default value: 4.
WT1231H ADVANCED COMMUNICATIONS & SENSING RegListen1 (0x0D) RegListen2 (0x0E) RegListen3 (0x0F) RegVersion (0x10) DATASHEET 7-6 ListenResolIdle rw 10 5-4 ListenResolRx rw 01 3 ListenCriteria rw 0 2-1 ListenEnd rw 01 0 7-0 ListenCoefIdle r rw 0 0xf5 Resolution of Listen mode Idle time (calibrated RC osc): 00 → reserved 01 → 64 us 10 → 4.1 ms 11 → 262 ms Resolution of Listen mode Rx time (calibrated RC osc): 00 → reserved 01 → 64 us 10 → 4.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 6.3.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 6.4.
WT1231H ADVANCED COMMUNICATIONS & SENSING RegOokPeak (0x1B) RegOokAvg (0x1C) DATASHEET 7-6 OokThreshType rw 01 5-3 OokPeakTheshStep rw 000 2-0 OokPeakThreshDec rw 000 7-6 OokAverageThreshFilt rw 10 5-0 7-0 OokFixedThresh r rw Selects type of threshold in the OOK data slicer: 00 → fixed 10 → average 01 → peak 11 → reserved Size of each decrement of the RSSI threshold in the OOK demodulator: 000 → 0.5 dB 001 → 1.0 dB 010 → 1.5 dB 011 → 2.0 dB 100 → 3.0 dB 101 → 4.0 dB 110 → 5.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 6.5.
WT1231H ADVANCED COMMUNICATIONS & SENSING RegIrqFlags2 (0x28) DATASHEET 7 FifoFull r 0 6 5 FifoNotEmpty FifoLevel r r 0 0 4 FifoOverrun rwc 0 3 PacketSent r 0 2 PayloadReady r 0 1 CrcOk r 0 0 7-0 RssiThreshold r rw 0 0xE4 * RegRxTimeout1 (0x2A) 7-0 TimeoutRxStart rw 0x00 RegRxTimeout2 (0x2B) 7-0 TimeoutRssiThresh rw 0x00 RegRssiThresh (0x29) Set when FIFO is full (i.e. contains 66 bytes), else cleared.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 6.6. Packet Engine Registers Table 28 Packet Engine Registers Name (Address) Bits Variable Name Mode Default Description Value 0x00 Size of the preamble to be sent (from TxStartCondition fulfilled).
WT1231H ADVANCED COMMUNICATIONS & SENSING PacketFormat rw 0 6-5 DcFree rw 00 4 CrcOn rw 1 3 CrcAutoClearOff rw 0 2-1 AddressFiltering rw 00 0 7-0 PayloadLength rw rw 0 0x40 RegNodeAdrs (0x39) 7-0 NodeAddress rw 0x00 Defines the packet format used: 0 → Fixed length 1 → Variable length Defines DC-free encoding/decoding performed: 00 → None (Off) 01 → Manchester 10 → Whitening 11 → reserved Enables CRC calculation/check (Tx/Rx): 0 → Off 1 → On Defines the behavior of the packet hand
WT1231H ADVANCED COMMUNICATIONS & SENSING RegFifoThresh (0x3C) RegPacketConfig2 (0x3D) 7 TxStartCondition rw FifoThreshold InterPacketRxDelay rw rw 3 2 RestartRx rw w 1 AutoRxRestartOn rw 0 AesOn rw 6-0 7-4 DATASHEET 1 * Defines the condition to start packet transmission : 0 → FifoLevel (i.e. the number of bytes in the FIFO exceeds FifoThreshold) 1 → FifoNotEmpty (i.e. at least one byte in the FIFO) 0001111 Used to trigger FifoLevel interrupt.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET RegAesKey14 (0x4B) 7-0 AesKey(23:16) w 0x00 14th byte of cipher key RegAesKey15 (0x4C) 7-0 AesKey(15:8) w 0x00 15th byte of cipher key RegAesKey16 (0x4D) 7-0 AesKey(7:0) w 0x00 16th byte of cipher key (LSB byte) 6.7.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 7. Application Information 7.1. Crystal Resonator Specification Table 31 shows the crystal resonator specification for the crystal reference oscillator circuit of the WT1231H. This specification covers the full range of operation of the WT1231H and is employed in the reference design.
WT1231H ADVANCED COMMUNICATIONS & SENSING DATASHEET 7.2.2. Manual Reset A manual reset of the WT1231H is possible even for applications in which VDD cannot be physically disconnected. Pin RESET should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the module. Figure 40. Manual Reset Timing Diagram Note whilst pin RESET is driven high, an over current consumption of up to ten milliamps can be seen on VDD.
WT1231H 7.3. Reference Design Please contact your representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors.
WT1231H 8. Packaging Information 8.1. Package Outline Drawing Figure 42.
WT1231H A 9. Ordering Information WT1231H—433 S2 Package Operation Band Mode Type P/N: WT1231H-315S2 WT1231H module at 315MHz band, SMD Package P/N: WT1231H-433S2 WT1231H module at 433MHz band, SMD Package P/N: WT1231H-868S2 WT1231H module at 868MHz band, SMD Package P/N: WT1231H-915S2 WT1231H module at 915MHz band, SMD PackageV Receiver category: Category 2 is standard performance level of receiver.
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