Specifications

Page 31
WT1231H
3.4.13. Bit Synchronizer
The Bit Synchronizer is a block that provides a clean and synchronized digital output, free of glitches. Its output is made
available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum
receiver performance its use when running Continuous mode is strongly advised.
Th
e Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in
RegBitrate.
Raw demodulator
output
(FSK or OOK)
BitSync Output To
pin DATA and
DCLK in continuous
mode
DATA
DCLK
Figure 13. Bit Synchronizer
Description
To ensure
correct operation of the Bit Synchronizer, the following conditions have to be satisfied:

A preamble (0x55 or 0xAA) of 12 bits
is required for synchronization (from the RxReady interrupt)

The subsequent payload bit stream must have at least one transition form '0' to '1' or '1' to '0 every 16 bits during data
transmission

The bit rate matching between the transmitter and the receiver must be better than 6.5 %.
Notes - If the Bit Rates of transmitter and receiver are known to be the same, the WT1231H will be able to receive an
infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction.
- If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the
BitSync can withstand can be estimated as follows:
- This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily
achievable (crystal tolerance is in the range of 50 to 100 ppm).
3.4.14. Frequency Error Indicator
This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency
of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the