IMS2 module user manual Project Name: IMS2 Author: Wistron NeWeb Corporation Revision: 1.
Product datasheet Contact Information Technical Support Website Company Website https://SupportIoT.wnc.com.tw www.wnc.com.tw Revision History Rev. # Author Summary of Changes Date 1.0 WNC First release 2017/07/14 1.
Product datasheet © Wistron NeWeb Corporation THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROPRIETARY AND IS THE EXCLUSIVE PROPERTY OF WNC AND SHALL NOT BE DISTRIBUTED, REPRODUCED, OR DISCLOSED IN WHOLE OR IN PART WITHOUT PRIOR WRITTEN PERMISSION FROM WNC. LIMITATION OF LIABILITY THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PURELY FOR DESIGN REFERENCE AND SUBJECT TO REVISION BY WNC AT ANY TIME.
Product datasheet Contents Contact Information .......................................................................................................................... 2 Revision History ............................................................................................................................... 2 1 Product Features ...................................................................................................................... 6 1.1 Features Description ...........................
Product datasheet 7.2 GP Compliance ................................................................................................................. 28 Initialisms ........................................................................................................................................
1 Product Features 1.1 Features Description The WNC IMS2 module includes the Sequans SQN3330 Cat. M1 baseband, a complete three LTE band (2/4/12) RF front-end, memory, and required circuitry to fulfill 3GPP E-UTRA (Long Term Evolution - LTE, Release 13 specifications) and AT&T Wireless LTE Cat. M1 UE specifications. The architecture block diagram of the IMS2 is presented in Figure 1-1 below. Figure 1-1. IMS2 block diagram Table 1-1.
Product datasheet Table 1-2.
Product datasheet 2 Pin Definitions 2.1 LGA Module Pin Diagram The IMS2 LGA module pin layout is illustrated below. Figure 2-1. IMS2 LGA module pin layout 2.2 LGA Module Pin Definitions The signals and all the related details are listed in the below table. Table 2-1. IMS2 module pin definition Pin No.
Product datasheet 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 80 81 82 83 84 85 Main antenna GND GND GND GND GND NC GND GND GND GND GND NC GND GND GND Power Power Power Power Power Power NC GND GND GPIO46 GPIO47 GPIO48 GPIO49 GND GND GPIO01 GPIO02 UART1_CTS UART1_RTS UART1_Rx UART1_Tx GND GND Main antenna port Ground Ground Ground Ground Ground Not connected Ground Ground Ground Ground Ground Not connected Ground Ground Ground Power Power Power Power
Product datasheet 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 201 202 203 NC NC NC GND GND GND UART0_CTS UART0_TX UART2_TX UART0_RX UART2_RX UART0_RTS UART2_RTS UART2_CTS FFF/FFH mode switch RFDATA5 RFDATA6 RFDATA7 ADC ADC GPIO08 UIM_VCC UIM DATA UIM CLK UIM RESET UIM DETECT NC GND GND WWAN_STATE Power on WAKEUP_OUT WAKEUP_IN RESET VREF JTAG TCK JTAG TDI JTAG TDO Not connected Not connected Not connected Ground Ground Groun
Product datasheet 204 205 206 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 JTAG_TMS JTAG_SRST_N NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND JTAG_TMS JTAG_SRST_N Not connected Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground □ Normal □ Internal Use Confidential □ Restricted Confidential 11 / 29
Product datasheet 3 Electrical Specifications 3.1 Electrical Operating Conditions 3.1.1 Detailed Information Table 3-1. Electrical operating conditions for the IMS2. Direction Minimum Typical Maximum VCC In 3.3 V 3.8 V 4.2 V IMS2 includes an integrated Power Manager enabling single and direct voltage supply from the battery and reducing the overall bill of materials. Layout Suggestion: Each power trace should possess sufficient line width to withstand its respective current listed in Table 3-2 below.
Product datasheet 3.2 Control Interfaces This section describes the power-on/off, wake-up, and reset interface for controlling the module. 3.2.1 Power-on Signal (TBD) The POWER_ON signal is an active low input signal used to enable or disable the module. Do not toggle the PERST# pin during power-on. This signal has the highest priority among the wakeup, the alarm signal, and the digital control pins. There are three possible states of the module: • Module Off: VCC is not present.
Product datasheet other side to activate sleep mode when not needed by toggling it low. • “WAKEUP_IN” (Host: Output, Modem: Input): • LOW: SoC does not require the MODEM (allowing it to sleep). • HIGH: SoC requires the MODEM or acknowledges it is ready following a wakeup request from the MODEM. • “WAKEUP_OUT” (Host: Input, Modem: Output): • LOW: The MODEM does not require the Host (allowing it to sleep).
Product datasheet 3.4 UIM Interface IMS2 modules provide a UIM_DETECT input pin for UIM connectors to detect a UIM card. When a UIM card is present, UIM_DETECT should be high (1.8 V). If the UIM card is absent, UIM_DETECT should be low. This is required to pull UIM_DETECT to VREF with a 470 kΩ resistor. A 0.1 μF and a 33 pF capacitor are recommended to place between UIM_VCC and Ground in parallel. We recommend placing a 33 pF capacitor between UIM_RESET, UIM_CLK, and UIM_DATA and Ground in parallel.
Product datasheet VOL Output low voltage VOH Output high voltage IRPU Input pull-up resistor current RPU Input pull-up resistance IRPD Input pull-down resistor current RPD Input pull-down resistance VH Input hysteresis IPAD Input leakage current, nontolerant IOZ Off-state leakage current IOL Sink current at VOL (max) IOH Source current at VOH (max) VSS 0.2 × PVDD_1V8 V 0.8 × PVDD_1V8 PVDD_1V8 V μA 15 32.4 μA 15 32.4 0.1 × PVDD_1V8 kΩ V –1 2 mA 4 mA 8 mA 12 mA 2 mA 4 mA 8 mA kΩ 1.11 2.
Product datasheet 3.6 JTAG Interface The IMS2 series contains one JTAG interface; leave JTAG pins floating if they are not used. Figure 3-4. JTAG schematic 3.7 Power Consumption This section describes the typical power consumption of the IMS2 (for reference). Table 3-4.
Product datasheet Power off Conditions Result Power off consumption The module is powered off. TBD 3.8 RF Performance Each IMS2 module has only one RF pad; developers must connect it via 50 Ω traces to the main board. Main antenna pad (Pin15) – Primary RX/TX path 3.8.1 RF Pad Design We recommended that a ground not be present under the surface of the RF pads in the layout. Details are included below. Layer2 has the same exclusion area as Layer1. Figure 3-5.
Product datasheet The RF trace between RF pads and antenna should as shorter as possible with 50ohm characteristic impedance. The characteristic impedance depends on the dielectric of PCB, the track width and the ground plane spacing. Microstrip type is required. The detail simulation as below.
Product datasheet The antenna should be 50ohm characteristic impedance with the return loss of better than -10dB at the operation band. The antenna gain would affect the radiated power and regulator test result.
Product datasheet 3.8.2 RF Matching Guide 1. Reserve the matching circuit as depicted in the topological structure below. 2. The matching circuit should be as close to the module as possible. The impedance (S11) should be close to 50 Ω, VSWR < 1.5. Primary Antenna RF connector Antenna matching Pin15 RF_1 IMS2 module Figure 3-6. RF matching guide 3.8.
Product datasheet 3.8.4 Band Support Table 3-5. Band support Band Uplink (MHz) Downlink (MHz) LTE Band 2 1,850–1,910 1,930–1,990 LTE Band 4 1,710–1,755 2,110–2,155 LTE Band 12 699–716 729–746 3.8.5 Bandwidth Support Table 3-6. Bandwidth support Bandwidth Band 1.4 MHz 3 MHz 5 MHz 10 MHz 15 MHz 20 MHz LTE Band 2 - - LTE Band 4 - - LTE Band 12 - - - - Note: The IMS2 supports 1.4 MHz and 3 MHz (not default settings). 3.8.
Product datasheet 3.8.7 RF Receiver Specifications Table 3-7. Conductive Rx sensitivity-3GPP Band Items Parameter L T E Unit Min. Max. –99.5 5 M Hz wit h4 RB s B a n d Typ. 2 LTE Band 4 RX Sensitivity 5 MHz with 4 RBs dBm –101.5 LTE Band 12 RX Sensitivity 5 MHz with 4 RBs dBm –98.5 Notes: 1. The RF receiver specification is defined at the LGA pad. 2. IMS2 fulfills 3GPP test standards. 3.
Product datasheet points cannot be rewritten on the SQN3330 platform.
Product datasheet 4 Mechanical Information 4.1 Physical Dimensions Device dimensions illustrated in Figure 4-1 and Figure 4-2 below. Figure 4-1. Top view Figure 4-2. Right view 4.2 Pin Dimensions The dimensions are illustrated in Figure 4-3, Figure 4-4, and Figure 4-5 below. Figure 4-3.
Product datasheet Figure 4-4. PIN dimensions Figure 4-5.
Product datasheet 4.3 Marking Information Note: Details will be provided in a future version of this document.
Product datasheet 5 Packing Information 5.1 Packing Information The module is delivered in tape-and-reel based on MPQ. Note: Module packing details will be provided in a future revision of this document. 5.2 Storage Conditions Note: Details will be provided in a future revision of this document. 6 PCB Mounting Guidelines 6.1 Mounting Considerations This section details the recommended reflow profile when the module is mounted onto other boards.
Product datasheet Initialisms Initialisms and Definitions Initialism Definition AC Alternating Current DC Direct Current ETSI European Telecommunications Standards Institute GND Ground GPIO General Purpose Input Output I/O Input/Output IoT Internet of Things I2C Inter-Integrated Circuit LGA Land Grid Array LTE Long Term Evolution N/A Not/Applicable OS Operating System PIN Personal Identification Number SIM Subscriber Identity Module SPI Serial Peripheral Interface UART Universal Asynchronous Receiver-Trans
