Product user manual Project Name: M18QAG Author: Wistron NeWeb Corporation Revision: 0.
HW Design Guidelines Contact Information Technical Support website https://SupportIoT.wnc.com.tw Company Website www.wnc.com.tw Revision History Rev. # Author Summary of Changes Date 0.1 WNC First release 2020/11/09 0.2 WNC Delete function block diagram and change 2020/11/17 FCC/IC statement 0.
HW Design Guidelines © Wistron NeWeb Corporation THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROPRIETARY AND IS THE EXCLUSIVE PROPERTY OF WNC AND SHALL NOT BE DISTRIBUTED, REPRODUCED, OR DISCLOSED IN WHOLE OR IN PART WITHOUT PRIOR WRITTEN PERMISSION FROM WNC. LIMITATION OF LIABILITY THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PURELY FOR DESIGN REFERENCE AND SUBJECT TO REVISION BY WNC AT ANY TIME.
HW Design Guidelines Contents Contact Information................................................................................................................. 2 Revision History........................................................................................................................ 2 Contents.................................................................................................................................... 4 1. Introduction.................................................
HW Design Guidelines 5. Mechanical and Environmental Certifications.................................................................. 23 5.1. PCBA Form Factor................................................................................................... 23 6. Design Guide.......................................................................................................................26 6.1. Power supply................................................................................................
HW Design Guidelines 1. Introduction The M18QAG module is LTE modems which incorporate an application CPU subsystem and peripheral interfaces and functions uniquely designed to address the power/performance/cost requirements of IoT and M2M applications. The CPU is based on Qualcomm’s MDM architecture which offers OFDMA-related software based signal processing capabilities that significantly exceed traditional communications ARM cores. M18QAG module provides a variety of interfaces including USB 2.
HW Design Guidelines PIN Personal Identification Number SIM Subscriber Identity Module SMA Surface Mount Antenna SPI Serial Peripheral Interface UART Universal Asynchronous Receiver-Transmitter UIM User Identity Module USB Universal Serial Bus Vref Voltage reference WCDMA Wideband Code Division Multiple Access WNC Wistron NeWeb Corporation 1.2. Features This section lists main features of M18QAG module support.
HW Design Guidelines Modem subsystem (MSS) Resource and power management (RPM) subsystem Optimized for M2M and IoT markets Interfaces – – – – – – – – – – HS USB 2.0 with integrated PHY SGMII interface Dual UART interfaces (4 bit and 2 bit) for data transfer and diagnostic tools SDC1/First SPI interface I2C/Second SPI interface USIM interface GPIOs ADC PCM/I2S JTAG interface 1.3. Environmental Specifications and Certifications 1.3.1.
HW Design Guidelines 1.3.2. Certifications The M18QAG module is certified to be compliant with PTCRB, FCC, IC. 1.3.3.
HW Design Guidelines 2. Electrical Specifications 2.1. Host interface pin assignments 2.1.1. LGA Pad Diagram Figure 1.
HW Design Guidelines 2.1.2. Pin Assignments I/O type description: AO : Analog Output AI : Analog Input DO : Digital Output DI : Digital Input Table 4. Pin interface family Description Interface Family Signal RF Interfaces RF_2 RF_GNSS RF_1 User Identity Module UIM_VCC UIM_DATA UIM_CLK UIM_RESET UIM_DETECT Data Interfaces- USB 2.
HW Design Guidelines UART1_RX UART1_TX Data Interfaces- UART2 UART2_RX UART2_TX Data Interfaces- I2C/2nd_ SPI I2C_SDA 2nd_SPI_EN_1 I2C_SCL 2nd_SPI_CLK SPI_MOSI NC SPI_MISO Data Interfaces- SDC1/1st_SPI SDC1_DATA_3 1st_SPIM_MOSI SDC1_DATA_2 1st_SPIM_MISO SDC1_DATA_1 1st_SPIM_EN_1 SDC1_DATA_0 1st_SPIM_CLK SDC1_CMD SDC1_CLK Module Control and State Interfaces WWAN_STATE POWER_ON WAKEUP_OUT WAKEUP_IN RESET Power and Ground VREF VCC GND General Purpose GPIO Receive for UART 1 Transmit for UART 1 DI DO Receiv
HW Design Guidelines ADC_CONVENTOR ADC_CONVENTOR AI PCM_DIN I2S_DATA0 PCM_DOUT I2S_DATA1 PCM_CLK I2S_SCK PCM_SYNC I2S_WS PCM_DIN I2S_DATA0 PCM_DOUT I2S_DATA1 PCM_CLK I2S_SCK PCM_SYNC I2S_WS DI DI/DO DO DI/DO DO DO DO DO RFU Reserved For Future Use - JTAG reset for debug JTAG clock input JTAG data input JTAG data output JTAG mode select input JTAG reset PS_HOLD DI DI DI DO DI DO DI AUDIO- PCM/I2S RFU- RFU Debug- JTAG JTAG_SRST_N JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N PS_HOLD Debug- Forc
HW Design Guidelines 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 GND GND GND GND RF_1 GND GND GND GND GND RF_2 GND GND GND GND GND NC GND GND GND GND GND NC GND GND GND VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 NC GND GND PCM_SYNC/GPIO46 GND GND GND GND RF_1 GND GND GND GND GND RF_2 GND GND GND GND GND NC GND GND GND GND GND NC GND GND GND VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 NC GND GND PCM_SYNC/GPIO46 3.3 3.3 3.3 3.3 3.3 3.3 1.
HW Design Guidelines 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 PCM_DIN/GPIO47 PCM_DOUT/GPIO48 PCM_CLK/GPIO49 GND GND GPIO01/Force USB BOOT Config*8 GPIO02 GPIO03 GPIO04 NC NC NC NC I2C_SDA PCM_DIN/GPIO47 PCM_DOUT/GPIO48 PCM_CLK/GPIO49 GND GND GPIO01/Force USB BOOT Config*8 GPIO02 GPIO03 GPIO04 SGMII_TX_P SGMII_TX_M SGMII_RX_P SGMII_RX_M I2C_SDA/ 2nd_SPI_EN_1 I2C_SCL I2C_SCL/ 2nd_SPI_CLK NC 2nd_SPI_MOSI NC 2nd_SPI_MISO GND GND GND GND RFFE1_DATA RFF
HW Design Guidelines 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 120 121 122 123 124 125 GND GND NC GPIO93 GPIO94 GPIO95 GPIO96 GPIO97 NC NC NC NC NC NC GND GND UART2_RX (UART 2) UART2_TX (UART 2) GND GND NC NC AD Converter NC NC 1st_SPI_MOSI 126 1st _SPI_MISO 127 1st _SPI_EN_1 128 1st _SPI_CLK 129 130 131 GPIO05 GPIO06 GPIO07 GND GND GPIO92 GPIO93 GPIO94 GPIO95 GPIO96 GPIO97 GPIO98 NC NC GPIO101 GPIO102 EPHY_RST_N GND GND UART2_RX (UART 2) UART2_TX (UART 2) GND GND SGMI
HW Design Guidelines 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 200 201 202 203 204 205 206 207 Notes: GPIO08 UIM_VCC UIM_DATA UIM_CLK UIM_RESET UIM_DETECT NC GND GND WWAN_STATE POWER_ON*4 WAKEUP_OUT*2 WAKEUP_IN*3 RESET VREF JTAG_SRST_N EPHY_INT_N/GPIO08 UIM_VCC UIM_DATA UIM_CLK UIM_RESET UIM_DETECT NC GND GND WWAN_STATE POWER_ON*4 WAKEUP_OUT*2 WAKEUP_IN*3 RESET VREF JTAG_SRST_N JTAG TCK JTAG TDI JTAG TDO JTAG_TMS JTAG TRST_N PS_HOLD NC JTAG TCK JTAG TDI JTAG TDO JTAG_TMS JTAG TRST_N P
HW Design Guidelines level shifter is recommended to transfer the voltage level to 1.8V. . Table 6. Digital I/O characteristics Below is the I/O default setting table to describe the level. It’s recommended to follow the pulling High or Low to choose a suitable GPIO for application. PU: Pull Up. PD: Pull Down NP: Non-Pull Pin No. 46 Table 7.
HW Design Guidelines 62 2nd_SPI_MOSI DI/DO PD 63 2nd_SPI_MISO DI/DO PD 80 UART1_CTS (UART1) DI/DO PD 81 UART1_RTS (UART1) DI/DO PD 82 UART1_RX (UART1) DI/DO PD 83 UART1_TX (UART1) DI/DO PD 92 GPIO92 DI/DO PD 93 GPIO93 DO NP 94 GPIO94 DI/DO PD 95 GPIO95 DI/DO PD 96 GPIO96 DI/DO PD 97 GPIO97 DI/DO PD 98 GPIO98 DI/DO PU 101 GPIO101 DI/DO PD 102 GPIO102 DI/DO PD 103 GPIO103 DI/DO PD 106 UART2_RX (UART2) DI/DO PD 107 UART2_TX (UART2) DI/DO P
HW Design Guidelines 3. Electrical Specifications 3.1. Power supply LTE module power input is VCC. The internal power chipset will transfer VCC to other power level. Table 8. Power supply voltage level Power Pin Name Pads Description Voltage Level (V) Min. Typ. Max. VCC VCC1 to VCC6 Nos. 37 to 42 Main Power Supply 3.3 3.8 4.2 The M18QAG includes an integrated power manager enabling single and direct voltage supply from the battery, reducing the overall bill of materials. The typical voltage 3.
HW Design Guidelines 3.2.2. Bandwidth support Table 10. Bandwidth support Bandwidth Band LTE Band 2 LTE Band 4 LTE Band 5 LTE Band 12 LTE Band 14 3.2.3. 1.4 MHz 3 MHz - - 5 MHz 10 MHz 15 MHz 20 MHz - - RF Transmit Specification Band Table 11. Conductive Tx output power Items Parameter Unit Min. Typ. Max. LTE Band 2 LTE Band 4 LTE Band 5 LTE Band 12 LTE Band 14 Max. TX Power Max. TX Power Max. TX Power Max. TX Power Max.
HW Design Guidelines WCDMA Band 2 WCDMA Band 5 RX Sensitivity RX Sensitivity - dBm dBm –104.7 –104.7 Note: 1. The RF Receiver Specification is defined at the LGA pad. 2. Meet 3GPP TS 36.521-1/TS 34.121-1 test standard. 3.2.5. GNSS receiver specifications Two GNSS SAW filter, LNA need to be used between the module and antenna. in 4. Software Interface 4.1. Support tools The M18QAG module is compatible with the following support tools: WNC M18QAG Series Connection Manager (WNCCM) 4.2.
HW Design Guidelines 5. Mechanical and Environmental Certifications 5.1. PCBA Form Factor M18QAG Series modules have the same dimensions: 34.5 mm (typ.) × 25.0 mm (typ.) × 2.45 mm (typ.) Figure 2.
HW Design Guidelines Figure 3.
HW Design Guidelines Figure 4.
HW Design Guidelines 6. Design Guide 6.1. Power supply LTE module power input is VCC. The internal power chipset will transfer VCC to other power level. Table 13. Power supply voltage level Power Pin Name Pads Description Voltage Level (V) Min. Typ. Max. VCC VCC1 to VCC6 Nos. 37 to 42 Main Power Supply 3.3 3.8 4.2 The M18QAG Series include an integrated power manager enabling single and direct voltage supply from the battery, reducing the overall bill of materials. The typical voltage 3.
HW Design Guidelines Layout Suggestion: The 22μF, 0.1uF, 12pF and 8pF capacitors are required to place near VCC pins as close as possible. Each power trace should possess sufficient line width to withstand its respective current listed in the table below: Net Name Current Value VCC(1–2) total VCC(3) total VCC(4–6) total UIM_VCC VREF 2A 100mA 1A 150 mA 300 mA 6.2. RF connections The M18QAG module has three RF pads; developers must connect them via 50 Ω traces to the main board.
HW Design Guidelines Figure 5. RF pad layout suggestion The characteristic impedance depends on the dielectric of PCB, the track width and the ground plane spacing. Microstrip type is required. The detail simulation as below. The RF trace of the test board which was used in the FCC test is defined as below.
HW Design Guidelines Microstrip trace 29 / 42
HW Design Guidelines 6.3. Interference and sensitivity This section includes tips to assist developers in identifying the interference that may affect M18QAG Series modules when used in systems. Interference from other wireless devices – Harmonics, inter-modulated signal generated from wireless devices that fall in RX ranges of the modules, may result in degraded RX performance. – It is highly recommended to check RX performance of entire systems within the shielding environment.
HW Design Guidelines Caution: DDR bus, LCD bus, DC-DC switching and PCM signals are easily to influence the WWAN and GNSS receiver performance, these signals must to be routed in the inner layer of the PCB and far away from the WWAN and GNSS receiver path. 6.4. Reflow This section details the recommended reflow profile when the module is mounted onto other boards. Temp. Region 1 Upper temp. region Lower temp.
HW Design Guidelines –34% Melt-out Time/230°C 46.91 -31% Max Temp 240.40 4% Total Time/217°C 81.18 -15% Gradient1 (100–150°C) 1.88 25% –36% –32% –48% 49.26 -7% 53.50 35% 48.18 –18% 6.59 241.34 13% 241.84 18% 241.32 13% 1.44 82.95 -8% 87.61 10% 81.24 –15% 6.43 1.91 28% 1.87 25% 1.86 24% 0.05 Process limit: Solder Paste Profile feature Gradient1 (Target = 1.5) (100 °C–150 °C) (Time period = 20 s) Preheat time from 140 °C to 190 °C Lead-free Min. 0 Max.
HW Design Guidelines Figure 6. Label drawing 8. Safety Recommendation Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
HW Design Guidelines communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: - Reorient or relocate the receiving antenna. - Increase the separation between the equipment and receiver.
HW Design Guidelines This module has been tested for compliance to FCC Part 22, 24, 27, 90 2.3 Summarize the specific operational use conditions The module is tested for standalone mobile RF exposure use condition. Any other usage conditions such as co-location with other transmitter(s) or being used in a portable condition will need a separate reassessment through a class II permissive change application or new certification. 2.4 Limited module procedures Not applicable. 2.
HW Design Guidelines 2.8 Label and compliance information The final end product must be labeled in a visible area with the following: “Contains FCC ID: NKRM18QAG”. The grantee's FCC ID can be used only when all FCC compliance requirements are met. 2.
HW Design Guidelines authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization.
HW Design Guidelines indésirable. Radiation Exposure Statement: This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with greater than 20cm between the radiator & your body. Déclaration d'exposition aux radiations: Cet équipement est conforme aux limites d'exposition aux rayonnements ISED établies pour un environnement non contrôlé.
HW Design Guidelines This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed and operated with greater than 20cm between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
HW Design Guidelines être utilisé sur le produit final. Dans ces circonstances, l'intégrateur OEM sera chargé de réévaluer le produit final (y compris l'émetteur) et l'obtention d'une autorisation distincte au Canada.
HW Design Guidelines End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed and operated with greater than 20cm between the antenna and users. The final end product must be labeled in a visible area with the following: “Contains IC: 4441A-M18QAG”.
HW Design Guidelines Le présent émetteur radio (IC: 4441A-M18QAG / Model: M18QAG) a été approuvé par ISED pour fonctionner avec les types d'antenne énumérés ci-dessous et ayant un gain admissible maximal. Les types d'antenne non inclus dans cette liste, et dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.