Product user manual Project Name: M18QF&M18QA series Author: Wistron NeWeb Corporation Revision: 1.
HW Design Guidelines Contact Information Technical Support website https://SupportIoT.wnc.com.tw Company Website www.wnc.com.tw Revision History Rev. # Author Summary of Changes Date 1.0 WNC First release 2019/8/12 1.
HW Design Guidelines © Wistron NeWeb Corporation THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PROPRIETARY AND IS THE EXCLUSIVE PROPERTY OF WNC AND SHALL NOT BE DISTRIBUTED, REPRODUCED, OR DISCLOSED IN WHOLE OR IN PART WITHOUT PRIOR WRITTEN PERMISSION FROM WNC. LIMITATION OF LIABILITY THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN IS PURELY FOR DESIGN REFERENCE AND SUBJECT TO REVISION BY WNC AT ANY TIME.
HW Design Guidelines Contents Contact Information................................................................................................................. 2 Revision History........................................................................................................................ 2 Contents.................................................................................................................................... 4 1. Introduction.................................................
HW Design Guidelines 2.7.5. I2C Interface................................................................................................ 35 2.7.6. UART Interface............................................................................................ 36 2.7.7. ADC Interface.............................................................................................. 36 3. RF Specifications.................................................................................................................
HW Design Guidelines 6.6. Thermal considerations.......................................................................................... 56 7. Regulatory Compliance and Certification..........................................................................58 7.1. Certification testing................................................................................................ 58 8. Packaging................................................................................................................
HW Design Guidelines 1. Introduction The M18QF/M18QA Series modules are LTE modems which incorporate an application CPU subsystem and peripheral interfaces and functions uniquely designed to address the power/performance/cost requirements of IoT and M2M applications. The CPU is based on Qualcomm’s MDM architecture which offers OFDMA-related software based signal processing capabilities that significantly exceed traditional communications ARM cores.
HW Design Guidelines PIN Personal Identification Number SIM Subscriber Identity Module SMA Surface Mount Antenna SPI Serial Peripheral Interface UART Universal Asynchronous Receiver-Transmitter UIM User Identity Module USB Universal Serial Bus Vref Voltage reference WCDMA Wideband Code Division Multiple Access WNC Wistron NeWeb Corporation 1.2. Features This section lists main features of M18QF/M18QA Series module support.
HW Design Guidelines Feature list: LTE 3GPP release 10 without Carrier Aggregation M18QF/M18QA: 3GPP, LTE Cat. 4 with 150/50 Mbps for DL/UL M14QF/M14QA: 3GPP, LTE Cat. 1 with 10/5 Mbps for DL/UL Supports LTE B2/4/5/12/13/14 Supports WCDMA B2/5, 3GPP release 8 Ultra-high-performance Cortex A7 microprocessor Modem subsystem (MSS) Resource and power management (RPM) subsystem Optimized for M2M and IoT markets Interfaces – – – – – – – – – – HS USB 2.
HW Design Guidelines 2. Electrical Specifications 2.1. Host interface pin assignments 2.1.1. LGA Pad Diagram Figure 1.
HW Design Guidelines 2.1.2. Pin Assignments I/O type description: AO : Analog Output AI : Analog Input DO : Digital Output DI : Digital Input Table 3. Pin interface family Description Interface Family Signal RF Interfaces RF_2 RF_GNSS RF_1 User Identity Module UIM_VCC UIM_DATA UIM_CLK UIM_RESET UIM_DETECT Data Interfaces- USB 2.
HW Design Guidelines UART1_RX UART1_TX Data Interfaces- UART2 UART2_RX UART2_TX Data Interfaces- I2C/2nd_ SPI I2C_SDA 2nd_SPI_EN_1 I2C_SCL 2nd_SPI_CLK SPI_MOSI NC SPI_MISO Data Interfaces- SDC1/1st_SPI SDC1_DATA_3 1st_SPIM_MOSI SDC1_DATA_2 1st_SPIM_MISO SDC1_DATA_1 1st_SPIM_EN_1 SDC1_DATA_0 1st_SPIM_CLK SDC1_CMD SDC1_CLK Module Control and State Interfaces WWAN_STATE POWER_ON WAKEUP_OUT WAKEUP_IN RESET Power and Ground VREF VCC GND General Purpose GPIO Receive for UART 1 Transmit for UART 1 DI DO Receiv
HW Design Guidelines ADC_CONVENTOR ADC_CONVENTOR AI PCM_DIN I2S_DATA0 PCM_DOUT I2S_DATA1 PCM_CLK I2S_SCK PCM_SYNC I2S_WS PCM_DIN I2S_DATA0 PCM_DOUT I2S_DATA1 PCM_CLK I2S_SCK PCM_SYNC I2S_WS DI DI/DO DO DI/DO DO DO DO DO RFU Reserved For Future Use - JTAG reset for debug JTAG clock input JTAG data input JTAG data output JTAG mode select input JTAG reset PS_HOLD DI DI DI DO DI DO DI AUDIO- PCM/I2S RFU- RFU Debug- JTAG JTAG_SRST_N JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N PS_HOLD Debug- Forc
HW Design Guidelines 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 GND GND GND GND RF_1 GND GND GND GND GND RF_2 GND GND GND GND GND NC GND GND GND GND GND NC GND GND GND VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 NC GND GND PCM_SYNC/GPIO46 GND GND GND GND RF_1 GND GND GND GND GND RF_2 GND GND GND GND GND NC GND GND GND GND GND NC GND GND GND VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 NC GND GND PCM_SYNC/GPIO46 3.3 3.3 3.3 3.3 3.3 3.3 1.
HW Design Guidelines 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 PCM_DIN/GPIO47 PCM_DOUT/GPIO48 PCM_CLK/GPIO49 GND GND GPIO01/Force USB BOOT Config*8 GPIO02 GPIO03 GPIO04 NC NC NC NC I2C_SDA PCM_DIN/GPIO47 PCM_DOUT/GPIO48 PCM_CLK/GPIO49 GND GND GPIO01/Force USB BOOT Config*8 GPIO02 GPIO03 GPIO04 SGMII_TX_P SGMII_TX_M SGMII_RX_P SGMII_RX_M I2C_SDA/ 2nd_SPI_EN_1 I2C_SCL I2C_SCL/ 2nd_SPI_CLK NC 2nd_SPI_MOSI NC 2nd_SPI_MISO GND GND GND GND RFFE1_DATA RFF
HW Design Guidelines 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 120 121 122 123 124 125 GND GND NC GPIO93 GPIO94 GPIO95 GPIO96 GPIO97 NC NC NC NC NC NC GND GND UART2_RX (UART 2) UART2_TX (UART 2) GND GND NC NC AD Converter NC NC 1st_SPI_MOSI 126 1st _SPI_MISO 127 1st _SPI_EN_1 128 1st _SPI_CLK 129 130 131 GPIO05 GPIO06 GPIO07 GND GND GPIO92 GPIO93 GPIO94 GPIO95 GPIO96 GPIO97 GPIO98 NC NC GPIO101 GPIO102 EPHY_RST_N GND GND UART2_RX (UART 2) UART2_TX (UART 2) GND GND SGMI
HW Design Guidelines 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 200 GPIO08 UIM_VCC UIM_DATA UIM_CLK UIM_RESET UIM_DETECT NC GND GND WWAN_STATE POWER_ON*4 WAKEUP_OUT*2 WAKEUP_IN*3 RESET VREF JTAG_SRST_N EPHY_INT_N/GPIO08 UIM_VCC UIM_DATA UIM_CLK UIM_RESET UIM_DETECT NC GND GND WWAN_STATE POWER_ON*4 WAKEUP_OUT*2 WAKEUP_IN*3 RESET VREF JTAG_SRST_N 1.7 1.7/2.7 1.7/2.7 1.7/2.7 1.7/2.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.8 1.8/3.0 1.8/3.0 1.8/3.0 1.8/3.0 1.8 0 0 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.
HW Design Guidelines *10. Reserve test points on pin52/86/88/106/107 for debug purpose if possible. *11. If voltage level of digital I/O from the other side is not compatible with module, level shifter is recommended to transfer the voltage level to 1.8V. Note2,3,4,8,9,10 must be followed otherwise module may fail or malfunction. Table 5. Digital I/O characteristics Below is the I/O default setting table to describe the level.
HW Design Guidelines 2nd_SPI_CLK 61 DI/DO PD 62 I2C_SDA/ 2nd_SPI_EN_1 2nd_SPI_MOSI DI/DO PD 63 2nd_SPI_MISO DI/DO PD 80 UART1_CTS (UART1) DI/DO PD 81 UART1_RTS (UART1) DI/DO PD 82 UART1_RX (UART1) DI/DO PD 83 UART1_TX (UART1) DI/DO PD 92 GPIO92 DI/DO PD 93 GPIO93 DO NP 94 GPIO94 DI/DO PD 95 GPIO95 DI/DO PD 96 GPIO96 DI/DO PD 97 GPIO97 DI/DO PD 98 GPIO98 DI/DO PU 101 GPIO101 DI/DO PD 102 GPIO102 DI/DO PD 103 GPIO103 DI/DO PD 106 UART2_RX (U
HW Design Guidelines 143 WAKEUP_OUT DI/DO PD 2.2. Power supply LTE module power input is VCC. The internal power chipset will transfer VCC to other power level. Table 7. Power supply voltage level Power Pin Name Pads Description Voltage Level (V) Min. Typ. Max. VCC VCC1 to VCC6 Nos. 37 to 42 Main Power Supply 3.3 3.8 4.2 The M18QF/M18QA Series include an integrated power manager enabling single and direct voltage supply from the battery, reducing the overall bill of materials.
HW Design Guidelines Layout Suggestion: The 22μF, 0.1uF, 12pF and 8pF capacitors are required to place near VCC pins as close as possible. Each power trace should possess sufficient line width to withstand its respective current listed in the table below: Net Name Current Value VCC(1–2) total VCC(3) total VCC(4–6) total UIM_VCC VREF 2A 100mA 1A 150 mA 300 mA 2.3. USB interface The M18QF/M18QA Series modules comply with USB 2.0 high-speed protocol. The USB input/output lines follow USB 2.
HW Design Guidelines Input Low Output High Output Low USB data positive (high-speed) Input High Input Low Output High Output Low 0 2.8 0.3 0 0.36 0 3.3 0.38 0.8 3.6 0.3 0.44 0.01 0.44 0.01 D– USB data negative (low-/full-speed) Input High Input Low Output High Output Low USB data negative (high-speed) Input High Input Low Output High Output Low 2 0 2.8 0.3 0 0.36 3.3 3.3 0.38 0 3.6 0.8 3.6 0.3 0.44 0.01 0.44 0.
HW Design Guidelines 2.4. SGMII interface The M18QF/M18QA Series modules integrate Ethernet MAC with SGMII interfaces with the following key features: IEEE 802.
HW Design Guidelines Signal lengths on the modules are tuned as below: Function Net Length (mil) SGMII SGMII_TX_P SGMII_TX_M SGMII_RX_P_C+SGMII_RX_P SGMII_RX_M_C+SGMII_RX_M 617.11 642.13 661.40 675.06 2.5. UIM interface M18QF/M18QA Series modules provide an UIM_DETECT input pin for UIM connector to detect UIM card. When UIM card is present, UIM_DETECT should be high (1.8V). If UIM card is absent, UIM_DETECT should be low. It’s required to pull UIM_DETECT to VREF with a 470k resistor. A 0.
HW Design Guidelines Figure 3. UIM card circuit example It’s highly suggested to make sure that SIM electrical characteristics can meet ETSI TS 102 221 requirement before going to certification like PTCRB.
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HW Design Guidelines 2.6. Control interface This section describes the power-on/off, wake-up and reset interface on how to control the module. 2.6.1. Power-on Signal The POWER_ON is an active Low input signal used to enable or disable the module. Do not toggle the PERST# pin during power-on. This signal has the highest priority over the wakeup, the alarms signals, and the digital control pins. There are three possible states of the module: Module Off - VCC is not present.
HW Design Guidelines An input to the POWER_ON pin shall trigger the transition from the Module Disabled to the Module Enabled state. See figure6, a low pulse(tlow > 0s) on POWER_ON pad will enable the module after VCC is applied. An input to the POWER_ON pin shall trigger the transition from the Module Enabled to the Module Disabled state. See figure6, after power on, a low pulse (tlow > 2s) on POWER_ON pin will disable (power-off) the module. Figure 4. Power ON/OFF timming 2.6.2.
HW Design Guidelines Each side can wake the other side by toggling wakeup signal high and allowing the other side to go to sleep when not needed by toggling it low. “WAKEUP_IN” (Host: Output, Modem: Input): – LOW: SoC does not require the MODEM (allowing it to sleep). – HIGH: SoC requires the MODEM or acknowledges it is ready following a wakeup request from the MODEM.
HW Design Guidelines 2.6.4. WWAN state Signal The WWAN state pin definition as below. WWAN state pin output “high” When device register to network, the WWAN state pin output “high”. WWAN state pin output “low” When device not to register to network, the WWAN state pin output “low”. 2.7. Digital interface This section provides required AC timing information related to module digital interfaces. 2.7.1.
HW Design Guidelines SPIM_MOSI – Output, data to slave SPIM_MISO – Input, data from slave Timing Figure 7. SPI timing parameters 2.7.3. PCM Interface M18QF/M18QA Series modules provide one PCM master digital audio interface. Keep PCM signal traces far away from noise and radiating signal on PCB Figure 8.
HW Design Guidelines Timing Figure 9. PCM timing diagram Figure 10.
HW Design Guidelines 2.7.4. I2S Interface PCM and I2S share the same pins on the modules, I2C only support master mode, keep I2S signal trace far away from noise and radiating signal on PCB Config1 Config2 PCM_SYNC PCM_DIN PCM_DOUT PCM_CLK I2S_WS I2S_DATA0 I2S_DATA1 I2S_SCK Figure 11.
HW Design Guidelines Figure 12. Figure 13. 2.7.5. I2S timing diagram I2S timing parameters I2C Interface M18QF/M18QA Series modules provide one I2C interface, I2C only support master mode. Figure 14.
HW Design Guidelines 2.7.6. UART Interface There are two UART interfaces on M18QF/M18QA Series: One is a 4 bit UART(UART1) for high-speed data transfer, max baud rate can be up to 4Mbps. Another is a 2 bit UART(UART2) for diagnostic tools and debugging, the default baud rate 115200bps is recommended. Figure 15. 2.7.7. UART connection (example) ADC Interface An Analog to Digital Converter (ADC) input is provided by the M18QF/M18QA Series. The converter is 16 bit resolution, ranging from 0.1 V to 1.
HW Design Guidelines 3. RF Specifications 3.1. RF connections The M18QF/M18QA Series modules have three RF pads; developers must connect them via 50 Ω traces to the main board. ANT0_TRX pad (Pin15) – Primary RX/TX path ANT1_DRX pad (Pin21) – Diversity path ANT_GNSS pad (Pin9) – GNSS path (For M18QF/M14QF*) Notes: * Due to the 2nd harmonic of B14 impacts GNSS reception performance seriously, embedded GNSS is not recommended to use for M18QA/M14QA.
HW Design Guidelines Figure 16. RF pad layout suggestion Figure 17. RF matching guide 3.2. Interference and sensitivity This section includes tips to assist developers in identifying the interference that may affect M18QF/M18QA Series modules when used in systems. Interference from other wireless devices – Harmonics, inter-modulated signal generated from wireless devices that fall in RX ranges of the modules, may result in degraded RX performance.
HW Design Guidelines away from high-speed switching signals. Furthermore, the trace from the module to the antenna should be as short as possible and must be shielded by complete grounding. – The M18QF/M18QA Series modules are well shielded; the high-speed elements (Ex.: DDR memory, LCD modules, DC-DC converter, PCM signal) on a system should have shielding reserved during the early stages of development. trace impedance for connection external shall be 50 ohms.
HW Design Guidelines Figure 18. GNSS design suggestion The following SAW filter and LNA components have been implemented by WNC development board. SAW filter1: Murata SAFFB1G56KB0F0AR15 LNA: INFINEON BGA824N6 SAW fiter2: Murata SAFFB1G56KB0F0AR15 If use module embedded GNSS, please follow above reference design. Pin146 (VREF, 1.8V) of module connects to the external LNA power supply pin. Pin129 (GPIO05) of module connects to external LNA enable control pin.
HW Design Guidelines The Notch filter reference design as below: 3.4. RF Specification 3.5.1 Band support Band Table 9.
HW Design Guidelines 3.5.2 Bandwidth support Band LTE Band 2 LTE Band 4 LTE Band 5 LTE Band 12 LTE Band 13 LTE Band 14 Table 10. Bandwidth support Bandwidth 1.4 MHz 3 MHz 10 MHz 15 MHz 20 MHz - 5 MHz - - - - - - 3.5.3 RF Transmit Specification Band Table 11. Conductive Tx output power Items Parameter Unit Min. Typ. Max. LTE Band 2 LTE Band 4 LTE Band 5 LTE Band 12 Max. TX Power Max. TX Power Max. TX Power Max.
HW Design Guidelines LTE Band 4 RX Sensitivity 10 MHz with 50 RBs dBm LTE Band 5 RX Sensitivity 10 MHz with 50 RBs dBm LTE Band 12 RX Sensitivity 10 MHz with 50 RBs dBm LTE Band 13 RX Sensitivity 10 MHz with 50 RBs dBm LTE Band 14 RX Sensitivity 10 MHz with 50 RBs dBm Band Items Parameter Unit WCDMA Band 2 RX Sensitivity dBm WCDMA Band 5 RX Sensitivity dBm Note: 1. The RF Receiver Specification is defined at the LGA pad. -102 -102 -103 -102 -102 Typ. –110 –110 –96.3 –94.3 –93.3 –93.3 –93.3 Max. –104.
HW Design Guidelines 25 RB with 50 RB with RBstart=25 RBstart=0 20 RB with 25 RB with 5035 731.5 RBstart=5 RBstart=0 20 RB with 25 RB with 12 5 5095 737.5 RBstart=5 RBstart=0 20 RB with 25 RB with 5155 743.5 RBstart=5 RBstart=0 20 RB with 25 RB with 5205 748.5 RBstart=5 RBstart=0 20 RB with 25 RB with 13 5 5230 751 RBstart=5 RBstart=0 20 RB with 25 RB with 5255 753.5 RBstart=5 RBstart=0 20 RB with 25 RB with 5305 760.
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HW Design Guidelines 4. Power 4.1. Power consumption This section describes typical power consumption of M18QF/M18QA Series for reference. The current data is measured at 3.8V VCC. Working Mode Table 15. LTE power consumption Conditions Result Only Module, no other device 1.50mA Airplane mode LTE standby(DRX=1.28 sec) Band2 –LTE Standby mode, DRX = 1.28 sec, BW=10MHz 2.24mA Band4 –LTE Standby mode, DRX = 1.28 sec, BW=10MHz 2.17mA Band5 –LTE Standby mode, DRX = 1.28 sec, BW=10MHz 2.
HW Design Guidelines interface by Iperf tool LTE Band13 Working mode Bandwidth 10MHz,TM3–DLRB 50–ULRB 50–IPV4-UDP , TX Power=23dbm,Downlink throughput is 72Mbps via USB interface by Iperf tool LTE Band14 Working mode 593mA Bandwidth 10MHz,TM3–DLRB 50–ULRB 50–IPV4-UDP , TX Power=23dbm,Downlink throughput is 72Mbps via USB interface by Iperf tool WCDMA standby(DRX=1.28 sec) 583mA Band2 –WCDMA Standby mode, DRX = 1.28 sec 1.94mA Band5 –WCDMA Standby mode, DRX = 1.28 sec 1.
HW Design Guidelines 5. Software Interface 5.1. Support tools The M18QF/M18QA Series modules are compatible with the following support tools: WNC M18QF/M18QA Series Connection Manager (WNCCM) 5.2. USB interface The M18QF/M18QA Series modules support 3GPP standard AT commands and proprietary AT commands; the MAL Manager SDK is also supported for Linux platforms. Refer to [WNC M18QF/M18QA Series] WNC MAL Manager Developer Guide for more information.
HW Design Guidelines 6. Mechanical and Environmental Certifications 6.1. PCBA Form Factor M18QF/M18QA Series modules have the same dimensions: 31.32 mm (typ.) × 23.5 mm (typ.) × 2.3 mm (typ.) Top view Figure 19.
HW Design Guidelines Figure 20.
HW Design Guidelines Figure 21.
HW Design Guidelines 6.2. Reflow This section details the recommended reflow profile when the module is mounted onto other boards. Temp. Region Upper temp. region Lower temp. region Conveyer band speed PWI = 91% 1 2 3 4 150 150 165 165 175 175 180 180 D31-1 Preheat from 140–190°C 85.34 –12% Melt-out Time/230°C 59.07 91% Max Temp 244.27 43% D31-2 5 6 7 195 205 230 195 205 230 95 cm/minute D31-3 D31-4 8 9 10 235 235 250 250 245 245 Temp. Difference 85.30 –13% 86.06 –8% 84.
HW Design Guidelines Total Time/217°C 90.55 22% Gradient1 (100–150°C) 1.91 27% 85.88 4% 90.09 20% 76.90 –32% 13.65 1.83 22% 1.93 29% 1.78 19% 0.15 Process limit: Solder Paste Lead-free Profile feature Gradient1 (Target = 1.5) (100 °C–150 °C) (Time period = 20 s) Preheat time from 140 °C to 190 °C Min. 0 Max. 3 Unit °C/S 70 105 S Time maintained above 230 °C 40 60 S Peak package body temperature 230 250 °C Time maintained above 217 °C 60 110 S 6.3.
HW Design Guidelines It is not recommended to place via or micro-via not covered by solder resist in an area of 0.3 mm around the pads unless it carries the same signal of the pad itself, see following figure. Holes in pad are allowed only for blind holes and not for through holes. 6.4. Labeling Figure26 shows label drawing of M18QF/M18QA Series modules.
HW Design Guidelines Figure 23. Label drawing 6.5. SMT Voids control 6.5.1. Mother board PCB thickness Thin mother board is prone to warping during SMT reflow, which creates voids when the module is soldered. Therefore, the thickness of the mother board needs to be larger than 1.2 mm, and the larger the size of the mother board, the larger the thickness. For example, 1.4mm, 1.6mm. 6.5.2. Stencil design The thickness of the stencil is at least 0.
HW Design Guidelines Figure 24. Stencil-foil drawing 6.6. Thermal considerations Grade Operating 3GPP compliant Functional work Industrial –40 °C~+85 °C –20 °C~+60 °C –40 °C~+85 °C Note: The temperature above refers to ambient temperature. Storage –40 °C ~+85 °C The case temperature of module shielding cover must be < 85 °C when integrated to prevent damage.
HW Design Guidelines transfer heat. If systems with M18QF/M18QA Series modules embedded intend to work under ambient temperatures as low as -40°C, it’s suggested that: 1. SIM Card need to be well arranged to make sure it is functional at the condition of ambient temperature as low as -40°C. 2. Adding heating circuit on board design, the circuit mainly consists of temperature sensing unit, heating element and control unit.
HW Design Guidelines 7. Regulatory Compliance and Certification 7.1.
HW Design Guidelines 8. Packaging 8.1. Tape-and-Reel Package The M18QF/M18QA Series modules are delivered in tape and reel. Figure 25.
HW Design Guidelines Figure 26. Figure 27.
HW Design Guidelines 8.2. Single Packaging for Samples Samples are packaged at 50 pcs. /box. There is no vacuum packaging. Samples must be baked for 8 hours at least at 85 °C before SMT. 8.3. MSL level The module MSL level is 3.
HW Design Guidelines 9. Safety Recommendation Be sure the use of this product is allowed in the country and in the environment required.
HW Design Guidelines following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
HW Design Guidelines Radiation Exposure Statement: This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. This module is intended for OEM integrators only. Per FCC KDB 996369 D03 OEM Manual v01 guidance, the following conditions must be strictly followed when using this certified module: KDB 996369 D03 OEM Manual v01 rule sections: 2.
HW Design Guidelines an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 20cm between the radiator & your body. If the module is installed in a portable host, a separate SAR evaluation is required to confirm compliance with relevant FCC portable RF exposure rules. 2.7 Antennas The following antennas have been certified for use with this module; antennas of the same type with equal or lower gain may also be used with this module.
HW Design Guidelines WCDMA V (B5) 824~849 3.2 3.2 LTE Band (2) 1850~1910 1.56 1.56 LTE Band (4) 1710~1755 1.62 1.62 LTE Band (5) 824~849 3.2 3.2 LTE Band (12) 698~716 1.49 1.49 LTE Band (13) 777~787 1.66 1.66 LTE Band (14) 788~798 1.60 1.60 2.8 Label and compliance information The final end product must be labeled in a visible area with the following: “Contains FCC ID: NKRM18QF”. The grantee's FCC ID can be used only when all FCC compliance requirements are met. 2.
HW Design Guidelines authorization is no longer considered valid and the FCC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate FCC authorization.
HW Design Guidelines indésirable. Radiation Exposure Statement: This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with greater than 20cm between the radiator & your body. Déclaration d'exposition aux radiations: Cet équipement est conforme aux limites d'exposition aux rayonnements ISED établies pour un environnement non contrôlé.
HW Design Guidelines IMPORTANT NOTE: In the event that these conditions can not be met (for example certain laptop configurations or co-location with another transmitter), then the Canada authorization is no longer considered valid and the IC ID can not be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining a separate Canada authorization.
HW Design Guidelines The end user manual shall include all required regulatory information/warning as show in this manual. Manuel d'information à l'utilisateur final L'intégrateur OEM doit être conscient de ne pas fournir des informations à l'utilisateur final quant à la façon d'installer ou de supprimer ce module RF dans le manuel de l'utilisateur du produit final qui intègre ce module.
HW Design Guidelines Gain (dBi) Band Freq. Range (MHz) Ant 1 Ant 2 (Main) (Aux) WCDMA II (B2) 1850~1910 1.56 1.56 WCDMA V (B5) 824~849 3.2 3.2 LTE Band (2) 1850~1910 1.56 1.56 LTE Band (4) 1710~1755 1.62 1.62 LTE Band (5) 824~849 3.2 3.2 LTE Band (12) 698~716 1.49 1.49 LTE Band (13) 777~787 1.66 1.66 LTE Band (14) 788~798 1.60 1.
