User's Manual
Table Of Contents
- Introduction
- Abbreviation
- Features
- Electrical Specifications
- Host interface pin assignments
- LGA Pad Diagram
- Pin Assignments
- Power supply
- USB interface
- SGMII interface
- UIM interface
- Control interface
- Power-on Signal
- Wake-up interface
- Reset Signal
- WWAN state Signal
- Digital interface
- JTAG Interface
- SPI Master Interface
- PCM Interface
- I2S Interface
- I2C Interface
- UART Interface
- ADC Interface
- RF Specifications
- RF connections
- Interference and sensitivity
- GNSS external circuit design
- RF Specification
- 3.5.1 Band support
- 3.5.2 Bandwidth support
- 3.5.3 RF Transmit Specification
- 3.5.4 RF Receiver Specification
- 3.5.5 GNSS Receiver Specification
- Power
- Power consumption
- Software Interface
- Support tools
- USB interface
- Mechanical and Environmental Certifications
- PCBA Form Factor
- Reflow
- PCB pad design
- Labeling
- SMT Voids control
- Mother board PCB thickness
- Stencil design
- Thermal considerations
- Regulatory Compliance and Certification
- Certification testing
- Packaging
- Tape-and-Reel Package
- Single Packaging for Samples
- MSL level
- Safety Recommendation
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71
HW Design Guidelines
132
GPIO08
EPHY_INT_N/GPIO08
1.7
1.8
1.9
133
UIM_VCC
UIM_VCC
1.7/2.7
1.8/3.0
1.9/3.3
134
UIM_DATA
UIM_DATA
1.7/2.7
1.8/3.0
1.9/3.3
135
UIM_CLK
UIM_CLK
1.7/2.7
1.8/3.0
1.9/3.3
136
UIM_RESET
UIM_RESET
1.7/2.7
1.8/3.0
1.9/3.3
137
UIM_DETECT
UIM_DETECT
1.7
1.8
1.9
138
NC
NC
-
-
-
139
GND
GND
-
0
-
140
GND
GND
-
0
-
141
WWAN_STATE
WWAN_STATE
1.7
1.8
1.9
142
POWER_ON
*4
POWER_ON*
4
1.7
1.8
1.9
143
WAKEUP_OUT
*2
WAKEUP_OUT*
2
1.7
1.8
1.9
144
WAKEUP_IN
*3
WAKEUP_IN*
3
1.7
1.8
1.9
145
RESET
RESET
1.7
1.8
1.9
146
VREF
VREF
1.7
1.8
1.9
200
JTAG_SRST_N
JTAG_SRST_N
1.7
1.8
1.9
201
JTAG TCK
JTAG TCK
1.7
1.8
1.9
202
JTAG TDI
JTAG TDI
1.7
1.8
1.9
203
JTAG TDO
JTAG TDO
1.7
1.8
1.9
204
JTAG_TMS
JTAG_TMS
1.7
1.8
1.9
205
JTAG TRST_N
JTAG TRST_N
1.7
1.8
1.9
206
PS_HOLD
PS_HOLD
1.7
1.8
1.9
207
NC
NC
-
-
-
Notes: *2. Do not pull pin143 WAKEUP_OUT to high; otherwise boot will fail.
*3. Pull Pin144 WAKEUP_IN to VREF with a 100k resistor and keep it high before
system boot process is complete.
*4. Pull pin142 POWER_ON to VREF with a 100k resistor for stability considerations.
*5. Refer to SGMII standard for more electronic characteristics.
*6. Refer to section 2.3, for more information please check USB2.0 standard
*7. Pull pin87 USB detect to VREF with a 100k resistor to enable module USB, pull
pin87 low to disable module USB, CPU USB PHY consumes some current when
USB is enabled.
*8. Do not pull pin52 to high before the system boot process is complete.
*9. Leave unused pins floating