User's Manual
Table Of Contents
- Introduction
- Abbreviation
- Features
- Electrical Specifications
- Host interface pin assignments
- LGA Pad Diagram
- Pin Assignments
- Power supply
- USB interface
- SGMII interface
- UIM interface
- Control interface
- Power-on Signal
- Wake-up interface
- Reset Signal
- WWAN state Signal
- Digital interface
- JTAG Interface
- SPI Master Interface
- PCM Interface
- I2S Interface
- I2C Interface
- UART Interface
- ADC Interface
- RF Specifications
- RF connections
- Interference and sensitivity
- GNSS external circuit design
- RF Specification
- 3.5.1 Band support
- 3.5.2 Bandwidth support
- 3.5.3 RF Transmit Specification
- 3.5.4 RF Receiver Specification
- 3.5.5 GNSS Receiver Specification
- Power
- Power consumption
- Software Interface
- Support tools
- USB interface
- Mechanical and Environmental Certifications
- PCBA Form Factor
- Reflow
- PCB pad design
- Labeling
- SMT Voids control
- Mother board PCB thickness
- Stencil design
- Thermal considerations
- Regulatory Compliance and Certification
- Certification testing
- Packaging
- Tape-and-Reel Package
- Single Packaging for Samples
- MSL level
- Safety Recommendation
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HW Design Guidelines
*10. Reserve test points on pin52/86/88/106/107 for debug purpose if possible.
*11. If voltage level of digital I/O from the other side is not compatible with module,
level shifter is recommended to transfer the voltage level to 1.8V.
Note2,3,4,8,9,10 must be followed otherwise module may fail or malfunction.
Table 5. Digital I/O characteristics
Below is the I/O default setting table to describe the level. It’s recommended to follow the
pulling High or Low to choose a suitable GPIO for application.
PU: Pull Up.
PD: Pull Down
NP: Non-Pull
Table 6. I/O default setting table
Pin
No.
Signal Name
Type
Default setting in
Normal mode
46
PCM_SYNC/GPIO46
DI /DO
PD
47
PCM_IN/GPIO47
DI /DO
PD
48
PCM_OUT/GPIO48
DI /DO
PD
49
PCM_CLK/GPIO49
DI /DO
PD
52
GPIO01
DI/DO
PD
53
GPIO02
DI/DO
PD
54
GPIO03
DI/DO
PD
55
GPIO04
DI/DO
PD
60
I2C_SCL/
DI/DO
PD