User's Manual
Table Of Contents
- Introduction
- Abbreviation
- Features
- Electrical Specifications
- Host interface pin assignments
- LGA Pad Diagram
- Pin Assignments
- Power supply
- USB interface
- SGMII interface
- UIM interface
- Control interface
- Power-on Signal
- Wake-up interface
- Reset Signal
- WWAN state Signal
- Digital interface
- JTAG Interface
- SPI Master Interface
- PCM Interface
- I2S Interface
- I2C Interface
- UART Interface
- ADC Interface
- RF Specifications
- RF connections
- Interference and sensitivity
- GNSS external circuit design
- RF Specification
- 3.5.1 Band support
- 3.5.2 Bandwidth support
- 3.5.3 RF Transmit Specification
- 3.5.4 RF Receiver Specification
- 3.5.5 GNSS Receiver Specification
- Power
- Power consumption
- Software Interface
- Support tools
- USB interface
- Mechanical and Environmental Certifications
- PCBA Form Factor
- Reflow
- PCB pad design
- Labeling
- SMT Voids control
- Mother board PCB thickness
- Stencil design
- Thermal considerations
- Regulatory Compliance and Certification
- Certification testing
- Packaging
- Tape-and-Reel Package
- Single Packaging for Samples
- MSL level
- Safety Recommendation
22
/
71
HW Design Guidelines
The layout design of this circuit on the carrier board should comply with the USB 2.0
high-speed protocol.
Layout suggestion:
Differential impedance: 90 Ω
Space to other signals should be at least 20 mils
Intra-lane length difference should be less than 150 mils
Maximum length for each trace:150 mm
Signals lengths on modules are tuned as below:
Function
Net
Length (mil)
USB
USB_Dp
545.54
USB_Dn
503.04
Input Low
0
0.8
Output High
2.8
3.3
3.6
Output Low
0.3
USB data positive (high-speed)
Input High
0.3
0.44
Input Low
0
0.01
Output High
0.36
0.38
0.44
Output Low
0
0.01
D–
USB data negative (low-/full-speed)
Input High
2
3.3
3.6
Input Low
0
0.8
Output High
2.8
3.3
3.6
Output Low
0.3
USB data negative (high-speed)
Input High
0.3
0.44
Input Low
0
0.01
Output High
0.36
0.38
0.44
Output Low
0
0.01