User's Manual
Table Of Contents
- Introduction
- Abbreviation
- Features
- Electrical Specifications
- Host interface pin assignments
- LGA Pad Diagram
- Pin Assignments
- Power supply
- USB interface
- SGMII interface
- UIM interface
- Control interface
- Power-on Signal
- Wake-up interface
- Reset Signal
- WWAN state Signal
- Digital interface
- JTAG Interface
- SPI Master Interface
- PCM Interface
- I2S Interface
- I2C Interface
- UART Interface
- ADC Interface
- RF Specifications
- RF connections
- Interference and sensitivity
- GNSS external circuit design
- RF Specification
- 3.5.1 Band support
- 3.5.2 Bandwidth support
- 3.5.3 RF Transmit Specification
- 3.5.4 RF Receiver Specification
- 3.5.5 GNSS Receiver Specification
- Power
- Power consumption
- Software Interface
- Support tools
- USB interface
- Mechanical and Environmental Certifications
- PCBA Form Factor
- Reflow
- PCB pad design
- Labeling
- SMT Voids control
- Mother board PCB thickness
- Stencil design
- Thermal considerations
- Regulatory Compliance and Certification
- Certification testing
- Packaging
- Tape-and-Reel Package
- Single Packaging for Samples
- MSL level
- Safety Recommendation
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HW Design Guidelines
2.4. SGMII interface
The M18QF/M18QA Series modules integrate Ethernet MAC with SGMII interfaces with the
following key features:
IEEE 802.3 compliance
Full duplex at 1 Gbps
Half/full duplex for 10/100 Mbps
Supports VLAN tagging
Supports IEEE 1588, Precision Time Protocol (PTP)
Can be used to connect to external Ethernet PHYs such as AR8033 or to an
external switch
The following figure illustrates an example of the additional logic connection between the
modules and the Ethernet chip. Refer to ENG-46158, Rev 1.8 for electrical and timing
specifications.
Figure 2. SGMII circuit example
Layout suggestion:
Differential impedance:100 Ω
Space to other signals: > 3x line width
Lane-to-lane space: > 3x line width
Intra-lane mismatch: < 0.7 mm