User's Manual

AVMD7300RX Module Datasheet PRELIMINARY v0p9
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 5 AVNERA PROPRIETARY & CONFIDENTIAL
AVMD7300 Pin Information
Table 1: AVMD7300RX Digital Input Pin Information (Standard 2mm Header)
Pin Number Pin Name Type Pin Description
1 V3.3PA Analog Power Future option – no connect
2 AGND Ground Isolated ground for PA
3 V3.3 Power Input Power input - (no connect if V5.0 is present)
4 V5.0 Power Input Power input – (no connect if V3.3 is present)
5 GND Ground Ground
6 PWR_BTN Power Button Input Turn on chip power when pulled low. Connect to
open drain output.
7 NC No connect
8 NC No connect
9 NC No connect
10 NC No connect
11 NC No connect
12 RESET_N Reset Input Drive low to force the chip into the RESET state
13 BCLK
PWM0
GPIO3
Multiplexed Digital I2S bit clock
PWM output for LED control
GPIO
14 LRCLK
PWM2
GPIO2
Multiplexed Digital I2S word clock
PWM output for LED control
GPIO
15 ADINOUT1
PWM1
GPIO1
Multiplexed Digital I2S data input/output
PWM output for LED control
GPIO
16 ADINOUT0
PWM0
GPIO0
Multiplexed Digital I2S data input/output
PWM output for LED control
GPIO
17 PWM2
MCLK
CFG_TESTMODE
Multiplexed Digital PWM output for LED control
Master clock output for I2S.
18 PWM0
ENC0_A
ADINOUT2
GPIO6
Multiplexed Digital PWM output for LED control
Rotary Encoder port input A
I2S data input/output
GPIO
19 PWM1
ENC0_B
GPIO7
Multiplexed Digital PWM output for LED control
Rotary Encoder port input B
GPIO
20 GND Ground Ground
21 NC No connect
22 NC No connect
23 S_MOSI
S_SCL
GPIO12
Multiplexed Digital SPI Slave MOSI (master out/slave in) data
TWI Slave SCL
GPIO
24 S_MISO
S_SDA
GPIO13
Multiplexed Digital SPI Slave MISO (master in/slave out) data
TWI Slave SDA
GPIO
25 S_SCLK
GPIO14
UART_RX
Multiplexed Digital SPI Slave serial clock output
GPIO
UART RX pin
26 S_SSB Multiplexed Digital SPI Slave SSB output