User's Manual

Product specification
12
88
SDIO1
SDCC1_DAT
A1
2.6V
I/O
SDIO1 data bit 1
2-16mA
89
SDIO1
SDCC1_CLK
2.6V
DO
Output clock for SDIO1 device
2-16mA
90
GPIO
GPIO3
1.8V
I/O, PU
Configurable I/O
1-8mA
91
GND
GND
GND
92
WLAN_PWR
_DOWN
2.6V
I/O, PU
Configurable I/O
2-16mA
93
UICC
USIM_RST
1.8V/2
.85V
DO
USIM reset
94
JTAG
JTAG_TDO
1.8V
Z
JTAG test data output
95
JTAG
JTAG_TDI
1.8V
DI, PU
JTAG test data input
96
power
output
VREG_MSM
P
2.6V
Output of the linear regulators
300mA
97
JTAG
JTAG_TRST
_N
1.8V
DI, PD
JTAG reset
98
USB UICC
USIM_D_P
1.8V/2
.85V
I/O
USB-UICC data plus line
99
USB UICC
USIM_D_M
1.8V/2
.85V
I/O
USB-UICC data minus line
100
GND
GND
GND
101
USB
USB_D_M
AI,AO
High-speed USB differential data,
(-) side
102
USB
USB_D_P
AI,AO
High-speed USB differential data,
(+) side
103
GND
GND
GND
104
power on
key
MSM_PON
1.8V
AI.PU
Connect to the keypad power
button. This signal is pulled up
internally to dVDD. When the QSC
device is off, pulling this pin low
initiates a powerup and generates an
interrupt.
105
ADC in
MPP4
AI,AO,
DI, DO
multipurpose pin
106
other
D2D_PS_HO
LD
DI
Baseband circuits drive this input
high to keep power on, low to shut
down
107
GND
GND
GND
108
GND
GND
GND
109
Speaker
SPKR_OUT_
P
AO
Speaker driver (+) output. Connect
directly to the speaker
500mW
110
Speaker
SPKR_OUT_
M
AO
Speaker driver (-) output. Connect
directly to the speaker
500mW
111
power
output
VREG_GP1
2.85V
P
Output of the linear regulators
150mA
112
power
output
VREG_GP2
2.9V
P
Output of the linear regulators
300mA
113
ADC in
MPP2
AI,AO,
multipurpose pin