User's Manual
Table Of Contents
- 2035-UM1xx.book
- Table of Contents
- List of Figures
- List of Tables
- Section 1: Introduction
- Section 2: Hardware System Overview
- Section 3: BCM2035 Usage Models
- Section 4: Hardware Configuration
- Section 5: Software Configuration
- Introduction
- Hardware Power-Up Sequence
- Boot ROM Power-Up Sequence
- Firmware Power-Up Sequence
- BCM2035 Mini-Drivers
- Loading Mini-Drivers from USB
- Load Mini-Drivers From UART
- SCO Configuration
- Frequency Trimming
- UART Sleep Mode Operation
- Section 6: Configuration Data File System
- Section 7: Vendor-Specific HCI Command Reference
- Section 8: ASCII Hex File Download Protocol
- Section 9: ASCII HEX File Format
- Section 10: Configuration Data Download Protocol
- Section 11: Configuration Data Image Format
- Section 12: UART Start-up Sequence
- Section 13: USB Start-up Sequence
9/29/2004 OV4F2
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User Manual BCM2035
04/23/03
Broadcom Corporation
Document 2035-UM100-R Hardware System Overview Page 5
Section 2: Hardware System Overview
INTRODUCTION
The BCM2035 is Bluetooth Core Specification version 1.1 compliant and designed for use in standard HCI
UART or HCI USB applications. Figure 2 shows a detailed hardware functional block diagram of the BCM2035.
The combination of the Bluetooth Baseband Controller (BBC), the Peripheral Transport Unit (PTU), and the
ROM based Microprocessor Unit (uPU) provide a complete lower layer Bluetooth protocol stack including the
Link Controller (LC), the Link Manager (LM), and the HCI interface.
Figure 2:
BCM2035 Hardware Functional Block Diagram
BCM2035 FUNCTIONAL BLOCK DIAGRAM
BCM2035 ASIC INTERFACE
PTU
Microprocessor Unit
Bluetooth Baseband Core RADIO
SYSTEM
CONTROL
Clock
Gen
XTAL
I/F
Transmiter
LOCAL
OSC
GEN
Receiver
MODEM
Digital
Modulator
Calibration
and
Control
Digital
Demod
Bit
Sync
PCM
USB
UART
8051
Core
RAM ROM
External
Memory
I/F
PIO
BSC
LNK IND
XTAL_PD
PMU
Link Control
Unit
FHC
Transmit Datapath
ACL
FIFO
SCO
FIFO
LMP
FIFO
Receive Datapath
ACL
FIFO
SCO
FIFO
LMP
FIFO
PCM_BCLK
PCM_IN
PCM_OUT
PCM_SYNC
USB_DETACH
USB_DN
USB_DP
BT_WAKE
HOST_WAKE
UART_CTS_N
UART_RTS_N
UART_TXD
UART_RXD
EEPROM_CLK
EEPROM_DATA
LPO_IN/LPO_RES
XTAL_PD
UP_ADDR[17:0]
UP_CS0_N
UP_DATA[7:0]
UP_CS1_N
UP_PSWR_N
UP_PSRD_N
UP_WR_N
UP_RD_N
TM[3:0]
RESET_N
BIAS48X
CPOUT_48X
XTAL_IN
XTAL_OUT
PA_OUTN
PA_OUTP
LNA_INN
LNA_INP
BIASCVAR
CPOUT
IBGVCO
VCTRL
Legend
Available only on 100pin package
Normal Signals
TX_PU_TDD_N/
LINK_IND/LPO_OUT
TX_PU_TDD
VOL
REG
REG_CTRL