User's Manual
Table Of Contents
- 2035-UM1xx.book
- Table of Contents
- List of Figures
- List of Tables
- Section 1: Introduction
- Section 2: Hardware System Overview
- Section 3: BCM2035 Usage Models
- Section 4: Hardware Configuration
- Section 5: Software Configuration
- Introduction
- Hardware Power-Up Sequence
- Boot ROM Power-Up Sequence
- Firmware Power-Up Sequence
- BCM2035 Mini-Drivers
- Loading Mini-Drivers from USB
- Load Mini-Drivers From UART
- SCO Configuration
- Frequency Trimming
- UART Sleep Mode Operation
- Section 6: Configuration Data File System
- Section 7: Vendor-Specific HCI Command Reference
- Section 8: ASCII Hex File Download Protocol
- Section 9: ASCII HEX File Format
- Section 10: Configuration Data Download Protocol
- Section 11: Configuration Data Image Format
- Section 12: UART Start-up Sequence
- Section 13: USB Start-up Sequence
9/29/2004 OV4F2
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BCM2035 User Manual
04/23/03
Broadcom Corporation
Page 12 Microprocessor Unit Document 2035-UM100-R
FAST CONNECTION
The BCM2035 supports page scan and inquiry scan modes that significantly reduce the average inquiry
response and connection times. These scanning modes are compatible with the Bluetooth version 1.1 page
and inquiry procedures and are designed to be forward compatible to Bluetooth version 1.x extension fast
connection mode.
MICROPROCESSOR UNIT
The Microprocessor Unit (uPU) runs software from the Link Control (LC) layer, up to the Host Controller
Interface (HCI). The microprocessor is an enhanced performance 8051 microcontroller. The uPU also consists
of the peripheral input/output, external memory interface (only available in the 100-pin and 104-pin package
for debug), 144 kbytes of ROM memory for program storage and boot ROM, 20 kbytes of RAM for data
scratchpad and patch RAM code, and interface to the PTU.
The internal boot ROM allows for flexibility during power-on reset to enable the same device to be used in
various configurations, including USB or UART and with or without an external serial EEPROM. At power-up,
the lower layer protocol stack is executed from the internal ROM memory.
External patches may be applied to the ROM based firmware to provide flexibility for bug fixes or features
additions. These patches may be downloaded from the host to the
BCM2035 through the USB or UART
transports, or by using an external serial EEPROM memory. The mechanism for downloading via UART or
USB is identical to the proven interface of the
BCM2035.
Optionally, for code development, a 100-pin or 104-pin version of the component is available which allows for
the interface to an external flash memory.
The 8051 core is object code compatible with the industry standard 8051 microcontroller.
PROGRAMMABLE I/O (PIO) PORT
The PIO or General Purpose I/O in the BCM2035 have been assigned to specific functions. Table 2 lists the
signal names and provides a brief description of the BCM2035 GPIO's.
Table 2: PIO/GPIO Assignment for the BCM2035
Pin Direction Description
GPIO0 BT_WAKE BT_WAKE and HOST_WAKE are side band signals used for low power
operation while using the UART transport.
GPIO1 XTAL_PD XTAL_PD is an output signal that can be used to shutdown system
clock for low power operation. This can be configured by the user as an
active high or an active low signal.
GPIO2 ADDR_17 This signal is used as an address pin to enable the 8051 processor to
access a 2M Flash. This option is only available on the 100-pin and
104-pin package.
GPIO3 HOST_WAKE BT_WAKE and HOST_WAKE are side band signals used for low power
operation while using the UART transport.