User's Manual
Table Of Contents
- 2035-UM1xx.book
- Table of Contents
- List of Figures
- List of Tables
- Section 1: Introduction
- Section 2: Hardware System Overview
- Section 3: BCM2035 Usage Models
- Section 4: Hardware Configuration
- Section 5: Software Configuration
- Introduction
- Hardware Power-Up Sequence
- Boot ROM Power-Up Sequence
- Firmware Power-Up Sequence
- BCM2035 Mini-Drivers
- Loading Mini-Drivers from USB
- Load Mini-Drivers From UART
- SCO Configuration
- Frequency Trimming
- UART Sleep Mode Operation
- Section 6: Configuration Data File System
- Section 7: Vendor-Specific HCI Command Reference
- Section 8: ASCII Hex File Download Protocol
- Section 9: ASCII HEX File Format
- Section 10: Configuration Data Download Protocol
- Section 11: Configuration Data Image Format
- Section 12: UART Start-up Sequence
- Section 13: USB Start-up Sequence
9/29/2004 OV4F2
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User Manual BCM2035
04/23/03
Broadcom Corporation
Document 2035-UM100-R Microprocessor Unit Page 13
EEPROM INTERFACE
The
BCM2035 provides the BSC (Broadcom Serial Control) master interface; the BSC is programmed by the
CPU to generate four different types of BSC transfers on the bus -- read-only, write-only, combined read/write,
and combined write-read. BSC supports both low-speed and fast mode devices. The BSC is compatible with
I2C slave devices, except that multiple I2C masters are not supported, and flexible wait state insertion by either
the master interface or slave devices are not support.
The EEPROM may contain configuration information concerning the customer application, including the
following: Fractional-N information, BD_ADDR, baud rate, USB enumeration information, SDP service record,
and file system information used for code, code patches, or data.
EXTERNAL MEMORY INTERFACE (100-PIN AND 104-PIN PACKAGE ONLY)
The memory interface (available only on the 100-pin and 104-pin package) allows 8051 microcontroller
accesses to two types of 8-bit wide external memory: Flash memory and SRAM. The interface can access 128
KB of external Flash memory, or 128 KB of external SRAM with no bank switching required.
RAM, ROM, AND PATCH MEMORY
The
BCM2035 has 20 kbytes of internal RAM, which is mapped between general-purpose scratch pad memory
and patch memory and 144 kbytes of ROM used for the lower layer protocol stack, test mode software, and
boot ROM. The patch memory capability enables the addition of code changes for purposes of feature
additions and bug fixes to the ROM memory.
GPIO4 TX_PU_TDD_N/
LINK_IND/
LPO_OUT
This pin has multiple functions. In normal mode, the default
configuration is TX_PU_TDD_N (see
“External TDD Switch
Control” on page 14
). In RF mode, the signal functions as the
LPO_OUT indicator. The signal can be configured by the user for Link
indication (LINK_IND).
GPIO5 EEPROM_CLK EEPROM_CLK and EEPROM_DATA signals are used to connect with
an external EEPROM with I2C interface.
GPIO6 EEPROM_DATA EEPROM_CLK and EEPROM_DATA signals are used to connect with
an external EEPROM with I2C interface.
GPIO7 USB_DETACH This signal is used by the
BCM2035 firmware to signal USB device
detachment and attachment to the HOST.
Table 2: PIO/GPIO Assignment for the BCM2035 (Cont.)
Pin Direction Description