User's Manual

9/29/2004 OV4F2
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User Manual BCM2035
04/23/03
Broadcom Corporation
Document 2035-UM100-R Peripheral Transport Unit Page 17
The USB Device Descriptor, Configuration Descriptor, and String Descriptor are fully programmable if the
default settings are not desired. This allows the end manufacturer to customize the descriptors that the
BCM2035 uses to identify itself on the USB port, including the Vendor ID and Product ID. Up to two sets of
custom descriptors can be supplied so that the BCM2035 may boot using one set of descriptors and then later
re-enumerate using the second set of descriptors. The custom USB descriptor information may be stored in
external EEPROM so that it is available at boot time.
The USB Descriptor Tables on the following pages contain detailed default descriptor information for the USB
interface.
UART
The UART physical interface is a standard, 4-wire interface (RX,TX, RTS, CTS) with adjustable baud rates
from 9600 bps to 1.5 Mbps. The interface features an automatic baud rate detection capability that will return
a baud rate selection from
Table 3. Alternatively, the baud rate may be selected via a vendor specific UART
HCI command. It has a 240-byte receive FIFO and a 240-byte transmit FIFO. The interface supports the
Bluetooth 1.1 UART HCI specification.
The baud rate of the BCM2035 UART is controlled by two values. The first is a UART Clock Divisor (also called
the DLBR register) that divides the 24 MHz reference clock by an integer multiple of 16. The second is a Baud
Rate Adjustment (also called the DHBR register) that is used to specify a number of 24 MHz clock cycles to
stuff in the first or second half of each bit time. Up to eight 24 MHz clock cycles can be inserted into the first
half of each bit time, and up to eight 24 MHz clock cycles can be inserted into the end of each bit time.
When setting the baud rate manually, the UART Clock Divisor is an 8-bit value that is stored as 256 - Desired
Divisor. For example, a desired divisor of 13 is stored as 256-13=243=0xF3.
The Baud Rate Adjustment is also an 8-bit value, of which the 4 most significant bits are the number of
additional clock cycles to insert in the first half of each bit time, and the 4 least significant bits are the number
of clock cycles to insert in the second half of each bit time. If either of these two values is over 8, it is rounded
to 8.
Table 3: Common Baud Rate Examples
Desired Baud
Rate (bps)
UART Clock Divisor
(256-Desired Divisor)
Baud Rate
Adjustment
Actual BCM2035 Baud
Rate (bps)
% Error
1500000 0XFF 0x00 1500000 0.00%
921600 0XFF 0x55 923077 0.16%
460800 0xFD 0x22 461538 0.16%
230400 0xFA 0x44 230796 0.17%
115200 0xF3 0x00 115385 0.16%
57600 0xE6 0x00 57692 0.16%
38400 0xD9 0x01 38400 0.00%
28800 0xCC 0x00 28846 0.16%
19200 0xB2 0x11 19200 0.00%
14400 0x98 0x00 14423 0.16%
9600 0x64 0x22 9600 0.00%