User's Manual

9/29/2004 OV4F2
C
O
N
F
I
D
E
N
T
I
A
L
F
O
R
W
I
S
T
R
O
N

C
O
R
P
O
R
A
T
I
O
N
BCM2035 User Manual
04/23/03
Broadcom Corporation
Page 28 PCM Configuration Document 2035-UM100-R
PCM CONFIGURATION
PCM HARDWARE SIGNALS
There are four signals used for the PCM interface; PCM_BCLK, PCM_SYNC, PCM_IN, and PCM_OUT. The
PCM_BCLK signal is the bit clock that controls the timing for the other three signals. PCM_SYNC is an 8kHz
sync pulse that marks the start of a new PCM frame. PCM_IN and PCM_OUT are the serial PCM data input
and output.
The hardware connection between the PCM interface and a CODEC are the same regardless of the
configuration of the PCM interface. The connections are shown in
Figure 12.
Figure 12: PCM Hardware Connectivity
The PCM interface on the
BCM2035 may be configured to operate in Master or Slave mode. In Master Mode,
the PCM_SYNC and PCM_BCLK signals are outputs from the
BCM2035. In Slave Mode, the PCM_SYNC and
PCM_BCLK signals are inputs to the
BCM2035 and should to be generated by the external CODEC.
The PCM_BCLK signal supports several clock rates as Master or Slave. Each clock rate allows for a different
number of available time slots for multiplexing audio CODEC connections. Table 5 lists the supported clock
rates and the number of time slots that are provided by each.
Table 5: Supported PCM Clock Rates
Supported Clock Rates Number of Time Slots Provided
128 kHz 1
256 kHz 2
512 kHz 4
1024 kHz 8
2048 kHz 16
PCM_IN
PCM_OUT
PCM_SYNC
PCM_BCLK
SYNC
CLK
DATA_IN
DATA_OUT
BCM2035CODEC