Datasheet

we-online.com
Würth Elektronik eiSos GmbH & Co. KG - Data Sheet - REV 1.0
15/31
WPMDH1302401 / 171032401
MagI³C Power Module
VDRM - Variable Step Down Regulator Module
DESIGN FLOW
Step 5. Select Soft-Start Capacitor (C
SS
)
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled,
thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8µA current source begins charging the
external soft-start capacitor. The soft-start capacitor can be calculated with:








(15)
with t
ss
= select soft-start time in (ms)
The use of a 4.7nF capacitor results in 0.5ms soft-start duration. This is a recommended minimum value.
As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. The soft-start capacitor
continues charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8V and 3.8V have no
effect on other circuit operation.
Note that high values of the C
SS
capacitance will cause more output voltage droop when a load transient goes across
the DCM-CCM boundary. Use equation (7) to find the DCM-CCM boundary load current for the specific operating
condition. If a fast load transient response is desired for steps between DCM and CCM mode the soft-start capacitor
value should be less than 0.018μF. Note that the following conditions will reset the soft-start capacitor by discharging
the SS input to ground with an internal 200μA current sink:
1. The enable input being “pulled low”
2. Thermal shutdown condition
3. Over-current fault
4. Internal VIN
UVLO
Step 6. Select Feed Forward Capacitor (C
FF
)
A feed-forward capacitor C
FF
is placed in parallel with R
FBT
which bypasses AC ripple directly to the feedback pin from
the output to support the internal ripple generator. This capacitor also affects load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple. A value of 22nF has been practically evaluated as best
performing. The feed forward capacitor C
FF
, should be located close to the FB pin.
Step 7. Optional: Select Enable Divider, R
ENT
, R
ENB
The enable input provides a precise 1.18V reference threshold to allow direct logic drive or connection to a voltage
divider from a higher enable voltage such as V
IN
. The enable input also incorporates 90mV (typ) of hysteresis
resulting in a falling threshold of 1.09V. The maximum recommended voltage into the EN pin is 6.5V. For applications
where the midpoint of the enable divider exceeds 6.5V, a small zener diode can be added to limit this voltage.
The function of the R
ENT
and R
ENB
divider shown in the application block diagram is to allow the designer to choose
an input voltage below which the circuit will be disabled. This implements the feature of programmable external under
voltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is
also useful in system designs for sequencing of output rails or to prevent early turn-on of the supply as the main input
voltage rail rises at power-up. Most systems will benefit by using the precision Enable threshold to establish a system
under voltage lockout. The recommended approach is to choose an input UVLO level that is higher than the target
regulated output voltage for the stage. Without an Enable divider, this series of devices will attempt to turn on around
3.5 Vin. This would not be useful for a stage that ultimately might be creating 5Vout. Operation of the module on input
voltage conditions below the nominal output should be avoided. Systems that don't implement the Enable divider will
turn in early during the rise of Vin and might not have monotonic rise in output voltage. Many systems need smooth
rise in supply voltage. In the case of sequencing supplies, the divider is connected to a rail that becomes active
earlier in the power-up cycle than the MagI³C power module output rail. The two resistors should be chosen based on
the following ratio: